LFXP2-5E-5TN144I Lattice, LFXP2-5E-5TN144I Datasheet
LFXP2-5E-5TN144I
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LFXP2-5E-5TN144I Summary of contents
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... LatticeXP2™ Family Handbook HB1004 Version 02.8, April 2011 ...
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... Tristate Register Block ............................................................................................................................ 2-30 © 2011 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... LatticeXP2 Internal Switching Characteristics.................................................................................................. 3-19 EBR Timing Diagrams...................................................................................................................................... 3-22 LatticeXP2 Family Timing Adders .................................................................................................................... 3-24 sysCLOCK PLL Timing .................................................................................................................................... 3-27 LatticeXP2 sysCONFIG Port Timing Specifications......................................................................................... 3-28 On-Chip Oscillator and Configuration Master Clock Characteristics................................................................ 3-29 Flash Download Time (from On-Chip Flash to SRAM) .................................................................................... 3-30 Flash Program Time......................................................................................................................................... 3-30 Flash Erase Time ...
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... Part Number Description.................................................................................................................................... 5-1 Ordering Information .......................................................................................................................................... 5-1 Lead-Free Packaging................................................................................................................................ 5-2 Conventional Packaging ........................................................................................................................... 5-5 Supplemental Information For Further Information ...................................................................................................................................... 6-1 LatticeXP2 Family Data Sheet Revision History Revision History ................................................................................................................................................. 7-1 Section II. LatticeXP2 Family Technical Notes LatticeXP2 sysIO Usage Guide Introduction ........................................................................................................................................................ 8-1 sysIO Buffer Overview ....................................................................................................................................... 8-1 Supported sysIO Standards ...
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... Appendix C. sysIO Attributes Using Preference File (ASCII File) .................................................................... 8-17 IOBUF ..................................................................................................................................................... 8-17 LOCATE.................................................................................................................................................. 8-17 USE DIN CELL........................................................................................................................................ 8-18 USE DOUT CELL.................................................................................................................................... 8-18 GROUP VREF ........................................................................................................................................ 8-18 LatticeXP2 sysCLOCK PLL Design and Usage Guide Introduction ........................................................................................................................................................ 9-1 Clock/Control Distribution Network .................................................................................................................... 9-1 LatticeXP2 Top Level View ................................................................................................................................ 9-1 Primary Clocks ................................................................................................................................................... 9-2 Secondary Clocks .............................................................................................................................................. 9-2 Edge Clocks ...
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... Lattice Semiconductor EPLLD Design Migration from LatticeECP2 to LatticeXP2 ....................................................................... 9-8 Dynamic Phase/Duty Mode....................................................................................................................... 9-8 Dynamic Phase Adjustment/Duty Cycle Select.................................................................................................. 9-9 PLL Usage in IPexpress™ ............................................................................................................................... 9-10 Configuration Tab.................................................................................................................................... 9-11 PLL Modes of Operation .................................................................................................................................. 9-13 PLL Clock Injection Removal .................................................................................................................. 9-13 PLL Clock Phase Adjustment.................................................................................................................. 9-14 IPexpress Output ...
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... WRITEMODE........................................................................................................................................ 10-54 GSR ...................................................................................................................................................... 10-54 LatticeXP2 High-Speed I/O Interface Introduction ...................................................................................................................................................... 11-1 DDR and DDR2 SDRAM Interfaces Overview................................................................................................. 11-1 Implementing DDR Memory Interfaces with LatticeXP2 Devices .................................................................... 11-3 DQS Grouping......................................................................................................................................... 11-3 DDR Software Primitives......................................................................................................................... 11-4 Memory Read Implementation ....................................................................................................................... 11-14 DLL Compensated DQS Delay Elements ............................................................................................. 11-14 DQS Transition Detect or Automatic Clock Polarity Select ...
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... Lattice Semiconductor Power Estimation and Management for LatticeXP2 Devices Introduction ...................................................................................................................................................... 12-1 Power Supply Sequencing and Hot Socketing................................................................................................. 12-1 Recommended Power-up Sequence ...................................................................................................... 12-1 Power Calculator Hardware Assumptions........................................................................................................ 12-1 Power Calculation Equations ........................................................................................................................... 12-1 Power Calculations ................................................................................................................................. 12-2 Using the Power Calculator.............................................................................................................................. 12-3 Starting the Power Calculator ................................................................................................................. 12-3 Creating a Power Calculator Project ...
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... Tag Memory ................................................................................................................................................... 14-15 Slave SPI Mode Operation.................................................................................................................... 14-16 User Flash...................................................................................................................................................... 14-16 Technical Support Assistance........................................................................................................................ 14-17 Revision History ............................................................................................................................................. 14-17 LatticeXP2 Configuration Encryption and Security Usage Guide Introduction ...................................................................................................................................................... 15-1 Encryption/Decryption Flow ............................................................................................................................. 15-1 Encrypting the JEDEC File............................................................................................................................... 15-1 ispLEVER Flow ....................................................................................................................................... 15-2 ispVM Flow.............................................................................................................................................. 15-2 Programming the Key into the Device ...
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... Lattice Semiconductor LatticeXP2 Soft Error Detection (SED) Usage Guide Introduction ...................................................................................................................................................... 16-1 SED Overview.................................................................................................................................................. 16-1 Basic SED and One-shot SED Modes ............................................................................................................. 16-2 Basic SED ............................................................................................................................................... 16-2 One-Shot SED ........................................................................................................................................ 16-2 Hardware Description....................................................................................................................................... 16-2 Signal Descriptions .......................................................................................................................................... 16-2 SEDCLKIN .............................................................................................................................................. 16-3 OSC_DIV ................................................................................................................................................ 16-3 SEDENABLE........................................................................................................................................... 16-3 SEDCLKOUT .......................................................................................................................................... 16-3 SEDSTART ...
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... Lattice Semiconductor Part 2: Program the Primary Pattern into LatticeXP2 Embedded Flash ............................................... 17-12 Reference Material......................................................................................................................................... 17-14 LatticeXP2 Bitstream File Format ......................................................................................................... 17-14 Implement SPI Flash Programming on ispVM System ......................................................................... 17-14 References..................................................................................................................................................... 17-15 Technical Support Assistance........................................................................................................................ 17-16 Revision History ............................................................................................................................................. 17-16 LatticeXP2 Hardware Checklist Introduction ...................................................................................................................................................... 18-1 Power Supply ...
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... Section I. LatticeXP2 Family Data Sheet DS1009 Version 01.7, April 2011 ...
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... Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the LatticeXP2 device. The ispLEVER tool extracts the timing from the routing and back-annotates it into the design for timing verification. ...
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... Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... PLLs PFU Blocks The core of the LatticeXP2 device is made up of logic blocks in two forms, PFUs and PFFs. PFUs can be pro- grammed to perform logic, arithmetic, distributed RAM and distributed ROM functions. PFF blocks can be pro- grammed to perform logic, arithmetic and ROM functions. Except where necessary, the remainder of this data sheet will use the term PFU to refer to both PFU and PFF blocks ...
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... Slice Routing PFU BLock Modes Logic, Ripple, ROM 2 LUT4s and 2 Registers Logic, ROM 2-3 Architecture LatticeXP2 Family Data Sheet LUT4 & LUT4 LUT4 CARRY Slice PFF Block Resources Modes Logic, Ripple, ROM Logic, Ripple, ROM Logic, Ripple, ROM 2 LUT4s Logic, ROM ...
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... F0, F1 LUT4 output register bypass signals Q0, Q1 Register outputs OFX0 Output of a LUT5 MUX OFX1 Output of a LUT6, LUT7, LUT8 FCO Slice 2 of each PFU is the fast carry chain output 2-4 LatticeXP2 Family Data Sheet SLICE OFX1 FF* To Routing LUT5 Mux ...
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... Dual Port RAM (PDPR) memory is created by using one slice as the read-write port and the other companion slice as the read-only port. The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the soft- ware will construct these using distributed memory primitives that represent the capabilities of the PFU. Table 2-3 shows the number of slices required to implement different distributed RAM primitives ...
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... Lattice Semiconductor Routing There are many resources provided in the LatticeXP2 devices to route signals individually or as busses with related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) seg- ments. The inter-PFU connections are made with x1 (spans two PFU), x2 (spans three PFU (spans seven PFU) connections ...
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... PLL LOCK to CLKI Clock Dividers LatticeXP2 devices have two clock dividers, one on the left side and one on the right side of the device. These are intended to generate a slower-speed system clock from a high-speed edge clock. The block operates in a ÷2, ÷4 or ÷ ...
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... LatticeXP2 devices derive primary clocks from four sources: PLL outputs, CLKDIV outputs, dedicated clock inputs and routing. LatticeXP2 devices have two to four sysCLOCK PLLs, located in the four corners of the device. There are eight dedicated clock inputs, two on each side of the device. Figure 2-6 shows the primary clock sources. ...
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... CLK DIV Clock Input Clock Input PLL Input GPLL Note: This diagram shows sources for the XP2-17 device. Smaller LatticeXP2 devices have two GPLLs. Clock Input Clock Input From Routing Primary Clock Sources to Eight Quadrant Clock Selection From Routing Clock Input ...
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... Lattice Semiconductor Secondary Clock/Control Sources LatticeXP2 devices derive secondary clocks (SC0 through SC7) from eight dedicated clock input pads and the rest from routing. Figure 2-7 shows the secondary clock sources. Figure 2-7. Secondary Clock Sources From Routing From Routing From Routing ...
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... Input From Routing CLKOP PLL GPLL CLKOS Input Sources for left edge clocks Note: This diagram shows sources for the XP2-17 device. Smaller LatticeXP2 devices have two GPLLs. Clock Input Clock Input From From Routing Routing Sources for top edge clocks ...
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... Lattice Semiconductor Primary Clock Routing The clock routing structure in LatticeXP2 devices consists of a network of eight primary clock lines (CLK0 through CLK7) per quadrant. The primary clocks of each quadrant are generated from muxes located in the center of the device. All the clock sources are connected to these muxes. Figure 2-9 shows the clock routing for one quadrant. ...
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... Lattice Semiconductor LatticeXP2-30 and smaller devices have six secondary clock regions. All devices in the LatticeXP2 family have four secondary clocks (SC0 to SC3) which are distributed to every region. The secondary clock muxes are located in the center of the device. Figure 2-12 shows the mux structure of the secondary clock routing ...
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... Secondary Clock Feedlines: 8 PIOs + 16 Routing 24:1 24:1 24:1 24:1 SC1 SC2 SC3 SC4 Clock/Control 4 High Fan-out Data Signals (SC4 to SC7) per Region Primary Clock 8 4 25:1 Routing 12 Vcc 1 2-14 Architecture LatticeXP2 Family Data Sheet 24:1 24:1 24:1 SC5 SC6 SC7 High Fan-out Data Clock to Slice ...
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... Secondary Clock Edge Clock Routing LatticeXP2 devices have eight high-speed edge clocks that are intended for use with the PIOs in the implementa- tion of high-speed interfaces. Each device has two edge clocks per edge. Figure 2-15 shows the selection muxes for these clocks. ...
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... All the EBR memory in the LatticeXP2 is shadowed by Flash memory. Optionally, initialization values for the mem- ory blocks can be defined using the Lattice ispLEVER tools. The initialization values are loaded into the Flash memory during device programming and into the SRAM at power up or whenever the device is reconfigured. This feature is ideal for the storage of a variety of information such as look-up tables and microprocessor code ...
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... Writes to EBR FPGA Logic Memory Cascading Larger and deeper blocks of RAMs can be created using EBR sysMEM Blocks. Typically, the Lattice design tools cascade memory transparently, based on specific design inputs. Single, Dual and Pseudo-Dual Port Modes In all the sysMEM RAM modes the input data and address for the ports are registered at the input of the memory array ...
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... Note that there are no reset restrictions if the EBR synchronous reset is used and the EBR GSR input is disabled. sysDSP™ Block The LatticeXP2 family provides a sysDSP block making it ideally suited for low cost, high performance Digital Sig- nal Processing (DSP) applications. Typical functions used in these applications include Bit Correlators, Fast Fourier Transform (FFT) functions, Finite Impulse Response (FIR) Filter, Reed-Solomon Encoder/Decoder, Turbo Encoder/ Decoder and Convolutional Encoder/Decoder ...
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... The user selects a function element for a DSP block and then selects the width and type (signed/unsigned) of its operands. The operands in the LatticeXP2 family sysDSP Blocks can be either signed or unsigned but not mixed within a function element. Similarly, the operand widths cannot be mixed within a block. DSP elements can be concatenated ...
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... Multiplicand Multiplier n Input Data Register B Signed A Signed B Shift Register B Out Shift Register Multiplier Input Data m Register Input To Register Multiplier Input To Register Multiplier Shift Register A Out 2-20 Architecture LatticeXP2 Family Data Sheet m+n m+n (default) x Output Pipeline Register CLK (CLK0,CLK1,CLK2,CLK3) CE (CE0,CE1,CE2,CE3) RST(RST0,RST1,RST2,RST3) ...
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... The output register is used to store the accumulated value. The Accumulators in the DSP blocks in LatticeXP2 family can be initialized dynamically. A registered overflow signal is also available. The overflow conditions are provided later in this document. Figure 2-21 shows the MAC sysDSP element. ...
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... Register Register Reg Input Pipeline Pipe To Add/Sub Register Register Reg Input Pipeline Pipe To Add/Sub Register Register Reg Shift Register A Out 2-22 Architecture LatticeXP2 Family Data Sheet CLK (CLK0,CLK1,CLK2,CLK3) CE (CE0,CE1,CE2,CE3) RST (RST0,RST1,RST2,RST3) m+n (default) Add/Sub Output m+n+1 m+n+1 (default) (default) m+n (default) ...
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... To Add/Sub0, Add/Sub1 Register Register Input Pipeline To Add/Sub0, Add/Sub1 Register Register Input Pipeline To Add/Sub0 Register Register Input Pipeline To Add/Sub1 Register Register Shift Register A Out 2-23 Architecture LatticeXP2 Family Data Sheet CLK (CLK0,CLK1,CLK2,CLK3) CE (CE0,CE1,CE2,CE3) RST(RST0,RST1,RST2,RST3) Add/Sub0 m+n+1 SUM m+n+2 m+n+2 m+n+1 Add/Sub1 Output ...
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... Signed Operation 2-24 Architecture LatticeXP2 Family Data Sheet Two’s Complement Two’s Complement Signed 9 Bits Signed 18 Bits 000000101 000000000000000101 111111010 111111111111111010 3 2 Carry signal is generated for 1 one cycle when this ...
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... DSP design cycle in Lattice FPGAs. Optimized DSP Functions Lattice provides a library of optimized DSP IP functions. Some of the IP cores planned for the LatticeXP2 DSP include the Bit Correlator, FFT functions, FIR Filter, Reed-Solomon Encoder/Decoder, Turbo Encoder/Decoder and Convolutional Encoder/Decoder. Please contact Lattice to obtain the latest list of available DSP IP cores. ...
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... LVDS outputs. All I/O pairs can operate as inputs. PIOA IOLT0 Tristate Register Block IOLD0 Output Register Block DI Input Control Register Muxes Block CLK1 CEO LSR GSR CLK0 CEI PIOB 2-26 Architecture LatticeXP2 Family Data Sheet PADA “T” sysIO Buffer PADB “C” ...
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... Output signals from the core for SDR and DDR operation Signals to Tristate Register block for DDR operation Dynamic input delay control bits Tristate signal from the core used in SDR operation Controls signal to the Output block LatticeXP2 High Speed I/O Interface. 2-27 Architecture ...
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... Q D D-Type D-Type DDRSRC SDR & Sync DDR Registers Registers D-Type D-Type D-Type Gearbox Configuration Bit 2-28 Architecture LatticeXP2 Family Data Sheet 2 INCK To DQS Delay Block INDD Clock Transfer Registers IPOS0A QPOS0A D-Type 1 /LATCH D-Type IPOS1A QPOS1A Q D-Type 1 D-Type /LATCH To Routing 2 ...
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... Clock Transfer Registers ECLK1 ECLK2 CLK1 (CLKB) DQSXFER * Shared with input register Latch Latch Note: Simplified version does not show CE and SET/RESET details 2-29 Architecture LatticeXP2 Family Data Sheet LatticeXP2 High D-Type 1 /LATCH D-Type Latch DDR Output D Q Registers D-Type /LATCH D-Type ...
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... Signal Descriptions table. The DQS signal from the bus is used to strobe the DDR data from the memory into input register blocks. For additional information on using DDR memory support please see TN1138, LatticeXP2 High Speed I/O Interface. 2-30 Architecture LatticeXP2 Family Data Sheet ...
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... Lattice Semiconductor Figure 2-28. DQS Input Routing (Left and Right) DQS Figure 2-29. DQS Input Routing (Top and Bottom) DQS LatticeXP2 Family Data Sheet PADA "T" PIO A LVDS Pair PADB "C" PIO B PADA "T" PIO A LVDS Pair PADB "C" PIO B PADA "T" ...
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... Left & Right Sides DQS Input Spans 18 PIOs Top & Bottom Sides I/O Bank 0 I/O Bank 1 DDR_DLL DDR_DLL (Right) (Left) I/O Bank 5 I/O Bank 4 2-32 Architecture LatticeXP2 Family Data Sheet ECLK1 ECLK2 Delayed DQS Polarity Control DQSXFER DQS Delay Control Bus ...
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... In a typical DDR memory interface design, the phase relationship between the incoming delayed DQS strobe and the internal system clock (during the READ cycle) is unknown. The LatticeXP2 family contains dedicated circuits to transfer data between these domains. To prevent set-up and hold violations, at the domain transfer between DQS (delayed) and the system clock, a clock polarity selector is used ...
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... LVCMOS, SSTL, HSTL, LVDS and LVPECL. sysIO Buffer Banks LatticeXP2 devices have eight sysIO buffer banks for user I/Os arranged two per side. Each bank is capable of sup- porting multiple I/O standards. Each sysIO bank has its own I/O supply voltage (V ...
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... MLVDS, BLVDS, LVPECL, RSDS, differential SSTL and differential HSTL. Tables 2-12 and 2-13 show the I/O stan- dards (together with their supply and reference voltages) supported by LatticeXP2 devices. For further information on utilizing the sysIO buffer to support a variety of standards please see TN1136, ...
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... Differential SSTL25 Class I, II Differential SSTL33 Class I, II Differential HSTL15 Class I Differential HSTL18 Class I, II LVDS, MLVDS, LVPECL, BLVDS, RSDS 1. When not specified, V can be set anywhere in the valid operating range (page 3-1). CCIO LatticeXP2 Family Data Sheet V (Nom.) V REF — — — ...
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... These capabilities make the LatticeXP2 ideal for many multiple power supply and hot-swap applications. IEEE 1149.1-Compliant Boundary Scan Testability All LatticeXP2 devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant Test Access Port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a serial scan path that can access all critical logic nodes ...
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... Guide. flexiFLASH Device Configuration The LatticeXP2 devices combine Flash and SRAM on a single chip to provide users with flexibility in device pro- gramming and configuration. Figure 2-33 provides an overview of the arrangement of Flash and SRAM configura- tion cells within the device. The remainder of this section provides an overview of these capabilities. See TN1141, LatticeXP2 sysCONFIG Usage Guide Figure 2-33 ...
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... Flash portion of the device. Serial TAG Memory LatticeXP2 devices offer 0.6 to 3.3kbits of Flash memory in the form of Serial TAG memory. The TAG memory is an area of the on-chip Flash that can be used for non-volatile storage including electronic ID codes, version codes, date stamps, asset IDs and calibration settings ...
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... For further information on SED support, please see TN1130, On-Chip Oscillator Every LatticeXP2 device has an internal CMOS oscillator that is used to derive a Master Clock (CCLK) for configu- ration. The oscillator and CCLK run continuously and are available to user logic after configuration is complete. The available CCLK frequencies are listed in Table 2-14 ...
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... Lattice Semiconductor Density Shifting The LatticeXP2 family is designed to ensure that different density devices in the same family and in the same pack- age have the same pinout. Furthermore, the architecture ensures a high success rate when performing design migration from lower density devices to higher density devices. In many cases also possible to shift a lower uti- lization design targeted for a high-density device to a lower density device ...
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... The minimum data retention, t RETENTION © 2011 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... CCIO V = 3.3V, 2.5V, 1.8V, 1.5V, 1.2V, CCIO V = 1.2V (MAX 3.3V, 2.5V, 1.8V, 1.5V, 1.2V, CCIO V = 1.2V (MAX 3-2 DC and Switching Characteristics LatticeXP2 Family Data Sheet Min. Typ. Max. — — +/- and CCAUX CCIO Min. Typ. Max. — — 10 — — 150 -30 — ...
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... Over Recommended Operating Conditions Parameter XP2-5 XP2-8 XP2-17 XP2-30 XP2-40 XP2-5 XP2-8 6 XP2-17 XP2-30 XP2-40 Power Estimation and Management for LatticeXP2 and I For csBGA, PQFP and TQFP packages the PLLs are CCAUX CCPLL. 3-3 DC and Switching Characteristics LatticeXP2 Family Data Sheet 5 Device Typical Units 14 ...
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... XP2-8 XP2-17 XP2-30 XP2-40 XP2-5 XP2-8 7 XP2-17 XP2-30 XP2-40 Power Estimation and Management for LatticeXP2 and I For csBGA, PQFP and TQFP packages the PLLs are powered independent of the CCAUX CCPLL. 3-4 DC and Switching Characteristics LatticeXP2 Family Data Sheet Typical 6 (25°C, Max. Supply) ...
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... XP2-8 XP2-17 XP2-30 XP2-40 XP2-5 XP2-8 7 XP2-17 XP2-30 XP2-40 8 Power Estimation and Management for LatticeXP2 and I . For csBGA, PQFP and TQFP packages the PLLs are powered independent of the CCAUX CCPLL 3-5 DC and Switching Characteristics LatticeXP2 Family Data Sheet Typical 6 (25°C, Max. Supply) ...
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... CCIO 3-6 DC and Switching Characteristics LatticeXP2 Family Data Sheet V (V) REF Min. Typ. — — — — — — — — — — — — — ...
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... REF - 0.125 V + 0.125 3.6 REF - 0.125 V + 0.125 3.6 REF - 0 0.1 3.6 REF - 0 0.1 3.6 REF - 0 0.1 3.6 REF 3-7 DC and Switching Characteristics LatticeXP2 Family Data Sheet Max. (V) Min. (V) I (mA) OL 20, 16, 0 0.4 CCIO 12 0 0.2 0.1 CCIO 20, 16, 0 0.4 CCIO 12 ...
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... LVDS25E The top and bottom sides of LatticeXP2 devices support LVDS outputs via emulated complementary LVCMOS out- puts in conjunction with a parallel resistor across the driver outputs. The scheme shown in Figure 3-1 is one possi- ble solution for point-to-point signals ...
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... VCCIO. The default drive current for LVCMOS33D output is 12mA with the option to change the device strength to 4mA, 8mA, 16mA or 20mA. Follow the LVCMOS33 specifications for the DC characteristics of the LVCMOS33D. DC and Switching Characteristics Description Typical 2.50 20 158 140 100 ) 1. 1. 0.35 P 1.25 100.5 6.03 3-9 LatticeXP2 Family Data Sheet Units V mA ...
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... Lattice Semiconductor BLVDS The LatticeXP2 devices support the BLVDS standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel external resistor across the driver outputs. BLVDS is intended for use when multi-drop and bi-directional multi-point differential signaling is required. The scheme shown in Figure 3-2 is one possible solution for bi-directional multi-point differential signals ...
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... Lattice Semiconductor LVPECL The LatticeXP2 devices support the differential LVPECL standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The LVPECL input standard is supported by the LVDS differential input buffer. The scheme shown in Figure 3-3 is one possible solution for point- to-point signals ...
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... Lattice Semiconductor RSDS The LatticeXP2 devices support differential RSDS standard. This standard is emulated using complementary LVC- MOS outputs in conjunction with a parallel resistor across the driver outputs. The RSDS input standard is sup- ported by the LVDS differential input buffer. The scheme shown in Figure 3-4 is one possible solution for RSDS standard implementation ...
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... Lattice Semiconductor MLVDS The LatticeXP2 devices support the differential MLVDS standard. This standard is emulated using complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The MLVDS input standard is supported by the LVDS differential input buffer. The scheme shown in Figure 3-5 is one possible solution for MLVDS standard implementation ...
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... DSP Functions 18x18 Multiplier (All Registers) 9x9 Multiplier (All Registers) 36x36 Multiply (All Registers) 18x18 Multiply/Accumulate (Input and Output Registers) 18x18 Multiply-Add/Sub-Sum (All Registers) DC and Switching Characteristics 1 Function Function 3-14 LatticeXP2 Family Data Sheet -7 Timing Units 4.4 ns 5.2 ns 5.6 ns 3 ...
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... Actual delays at nominal temperature and voltage for best case process, can be much better than the values given in the tables. The ispLEVER design tool can provide logic timing numbers at a particular temperature and voltage. DC and Switching Characteristics Function 3-15 LatticeXP2 Family Data Sheet -7 Timing Units 198 MHz 221 ...
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... XP2-17 — XP2-30 — XP2-40 — XP2-5 0.00 XP2-8 0.00 XP2-17 0.00 XP2-30 0.00 XP2-40 0.00 3-16 DC and Switching Characteristics LatticeXP2 Family Data Sheet -6 -5 Max. Min. Max. Min. Max. 3.80 — 4.20 — 3.80 — 4.20 — 3.80 — 4.20 — ...
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... Lattice Semiconductor LatticeXP2 External Switching Characteristics (Continued) Parameter Description Clock to Data Hold - PIO Input t HE Register Clock to Data Setup - PIO Input t SU_DELE Register with Data Input Delay Clock to Data Hold - PIO Input t H_DELE Register with Input Data Delay Clock Frequency of I/O and PFU ...
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... Lattice Semiconductor LatticeXP2 External Switching Characteristics (Continued) Parameter Description Clock to Data Hold - PIO Input t H_DELPLL Register with Input Data Delay 2 3 DDR and DDR2 I/O Pin Parameters Data Valid After DQS t DVADQ (DDR Read) Data Hold After DQS t DVEDQ ...
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... DC and Switching Characteristics LatticeXP2 Family Data Sheet Min. Max. Min. Max. — 0.238 — 0.260 — 0.399 — 0.494 — 0.769 — 0.818 0.151 — ...
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... DC and Switching Characteristics LatticeXP2 Family Data Sheet 1 (Continued Min. Max. Min. Max. — 0.419 — 0.452 0.035 0.035 0.035 0.035 — 3.142 — ...
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... Max. -0.787 — 4.896 — -1.439 — — 4.513 — 2.153 — 0.569 -0.270 — 0.306 — 3-21 DC and Switching Characteristics LatticeXP2 Family Data Sheet 1 (Continued Min. Max. Min. Max. -0.890 — -0.994 — 5.413 — 5.931 — -1.604 — -1.770 — ...
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... Figure 3-7. Read/Write Mode with Input and Output Registers CLKA CSA WEA ADA t DIA DOA (Regs CO_EBR Invalid Data Mem(n) data from previous read output is only updated during a read cycle 3-22 DC and Switching Characteristics LatticeXP2 Family Data Sheet CO_EBR CO_EBR COO_EBR COO_EBR D1 D0 ...
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... Data from Prev Read DOA or Write Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock. Three consecutive writes ACCESS ACCESS ACCESS D0 D1 3-23 DC and Switching Characteristics LatticeXP2 Family Data Sheet ACCESS ...
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... HSTL18_I HSTL_18 class I 8mA drive HSTL18_II HSTL_18 class II HSTL18D_I Differential HSTL 18 class I 8mA drive HSTL18D_II Differential HSTL 18 class Over Recommended Operating Conditions Description 4 3-24 DC and Switching Characteristics LatticeXP2 Family Data Sheet - -0.26 -0.11 0.04 -0.26 -0.11 0.04 -0.26 -0.11 0.04 -0.26 -0 ...
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... LVCMOS 3.3 12mA drive, slow slew rate LVCMOS33_16mA LVCMOS 3.3 16mA drive, slow slew rate LVCMOS33_20mA LVCMOS 3.3 20mA drive, slow slew rate (Continued) Over Recommended Operating Conditions Description 3-25 DC and Switching Characteristics LatticeXP2 Family Data Sheet - 0.32 0.69 1.06 0.32 0.69 1.06 -0.25 ...
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... LVCMOS timing measured with the load specified in Switching Test Condition table. 3. All other standards tested according to the appropriate specifications. 4. These timing adders are measured with the recommended resistor values. Timing (Continued) Over Recommended Operating Conditions Description 3-26 DC and Switching Characteristics LatticeXP2 Family Data Sheet - 1.05 1.43 1.81 0.78 1.15 1.52 ...
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... MHz < f < 400 MHz OUT f < 100 MHz OUT N/M = integer At 90 435 MHz MHz 90% to 90% 10% to 10% 10% to 90% 3-27 DC and Switching Characteristics LatticeXP2 Family Data Sheet Min. Typ. Max. 10 — 435 10 — 435 0.078 — 217.5 3.3 — ...
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... Lattice Semiconductor LatticeXP2 sysCONFIG Port Timing Specifications Parameter sysCONFIG POR, Initialization and Wake Up t Minimum Vcc to INITN High ICFG t Time from t to valid Master CCLK VMC ICFG t PROGRAMN Pin Pulse Rejection PRGMRJ t PROGRAMN Low Time to Start Configuration PRGM 1 t PROGRAMN High to INITN High Delay ...
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... VCC PROGRAMN DONE INITN CSSPIN CCLK SISPI SOSPI Over Recommended Operating Conditions Min. Selected value -30% Selected value +30% 40 Capture CFGx … Opcode 3-29 DC and Switching Characteristics LatticeXP2 Family Data Sheet Max. Units MHz … … 127 128 Address Ignore Valid Bitstream ...
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... Erase Time Flash Density TAG Main Array TAG Main Array TAG Main Array TAG Main Array TAG Main Array 3-30 DC and Switching Characteristics LatticeXP2 Family Data Sheet Typ. Max. — 1.8 2.1 — 1.9 2.3 — 1.7 2.0 — 2.0 2.1 — ...
Page 86
... BSCAN test update register, falling edge of clock to valid enable BTUPOEN Timing v. A 0.12 Over Recommended Operating Conditions EBR Density (Bits) Time (Typ.) 166K 221K 276K 387K 885K Over Recommended Operating Conditions Parameter 3-31 DC and Switching Characteristics LatticeXP2 Family Data Sheet Units 1.5 s 1.5 s 1.5 s 2.0 s 3.0 s Min. Max. — ...
Page 87
... Figure 3-10. JTAG Port Timing Waveforms TMS TDI t BTCPH TCK TDO Data to be captured from I/O Data to be driven out to I/O DC and Switching Characteristics t t BTS BTH t BTCPL t t BTCO BTCOEN BTCRH t BTCRS Data Captured t t BTUPOEN BUTCO 3-32 LatticeXP2 Family Data Sheet t BTCP t BTCODIS BTUODIS ...
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... Includes Test Fixture and Probe Capacitance 1M 1M 100 100 3-33 DC and Switching Characteristics LatticeXP2 Family Data Sheet Test Poi nt C Timing Ref. L LVCMOS 3.3 = 1.5V LVCMOS 2 CCIO 0pF LVCMOS 1 CCIO LVCMOS 1 CCIO LVCMOS 1 ...
Page 89
... TCK TDI © 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com ...
Page 90
... Chip select in Slave SPI mode. This pin has a weak internal pull-up. Test Output Enable tristates all I/O pins when driven low. This pin has a weak I internal pull-up, but when not used an external pull- mended. 4-2 Pinout Information LatticeXP2 Family Data Sheet Description is recom- CC is recommended. ...
Page 91
... In some packages, all the potential DDR data (DQ) pins may not be available. PIC numbering definitions are provided in the “Signal Names” column of the Signal Descriptions table. LatticeXP2 Family Data Sheet DDR Strobe (DQS) and PIO Within PIC Data (DQ) Pins ...
Page 92
... Pinout Information LatticeXP2 Family Data Sheet XP2-17 XP2-30 208 256 484 256 484 672 PQFP ftBGA fpBGA ftBGA fpBGA fpBGA 146 201 358 201 363 472 57 77 135 77 137 180 ...
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... Minimum requirement to implement a fully functional 8-bit wide DDR bus. Available DDR interface consists of at least 12 I/Os (1 DQS + 1 DQSB + 8 DQs + Bank VREF1). Logic Signal Connections Package pinout information can be found under “Data Sheets” on the LatticeXP2 product page of the Lattice web- site a www.latticesemi.com/products/fpga/xp2 and in the Lattice ispLEVER software. Thermal Management Thermal management is recommended as part of any sound FPGA design methodology ...
Page 94
... August 2008 Part Number Description LFXP2 – – X XXXXX X Device Family XP2 Logic Capacity LUTs LUTs 17 = 17K LUTs 30 = 30K LUTs 40 = 40K LUTs Supply Voltage E = 1.2V Speed 5 = Slowest Fastest Ordering Information The LatticeXP2 devices are marked with a single temperature grade, either Commercial or Industrial, as shown below. © ...
Page 95
... LFXP2-8E-5MN132C 1.2V LFXP2-8E-6MN132C 1.2V LFXP2-8E-7MN132C 1.2V LFXP2-8E-5TN144C 1.2V LFXP2-8E-6TN144C 1.2V LFXP2-8E-7TN144C 1.2V LFXP2-8E-5QN208C 1.2V LFXP2-8E-6QN208C 1.2V LFXP2-8E-7QN208C 1.2V LFXP2-8E-5FTN256C 1.2V LFXP2-8E-6FTN256C 1.2V LFXP2-8E-7FTN256C 1.2V Part Number Voltage LFXP2-17E-5QN208C 1.2V LFXP2-17E-6QN208C 1.2V LFXP2-17E-7QN208C 1.2V LFXP2-17E-5FTN256C 1.2V LFXP2-17E-6FTN256C 1.2V LFXP2-17E-7FTN256C 1.2V LFXP2-17E-5FN484C 1.2V LFXP2-17E-6FN484C 1 ...
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... Voltage LFXP2-40E-5FN484C 1.2V LFXP2-40E-6FN484C 1.2V LFXP2-40E-7FN484C 1.2V LFXP2-40E-5FN672C 1.2V LFXP2-40E-6FN672C 1.2V LFXP2-40E-7FN672C 1.2V Part Number Voltage LFXP2-5E-5MN132I 1.2V LFXP2-5E-6MN132I 1.2V LFXP2-5E-5TN144I 1.2V LFXP2-5E-6TN144I 1.2V LFXP2-5E-5QN208I 1.2V LFXP2-5E-6QN208I 1.2V LFXP2-5E-5FTN256I 1.2V LFXP2-5E-6FTN256I 1.2V Part Number Voltage LFXP2-8E-5MN132I 1.2V LFXP2-8E-6MN132I 1.2V LFXP2-8E-5TN144I 1.2V LFXP2-8E-6TN144I 1 ...
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... LFXP2-17E-6FTN256I 1.2V LFXP2-17E-5FN484I 1.2V LFXP2-17E-6FN484I 1.2V Part Number Voltage LFXP2-30E-5FTN256I 1.2V LFXP2-30E-6FTN256I 1.2V LFXP2-30E-5FN484I 1.2V LFXP2-30E-6FN484I 1.2V LFXP2-30E-5FN672I 1.2V LFXP2-30E-6FN672I 1.2V Part Number Voltage LFXP2-40E-5FN484I 1.2V LFXP2-40E-6FN484I 1.2V LFXP2-40E-5FN672I 1.2V LFXP2-40E-6FN672I 1.2V LatticeXP2 Family Data Sheet Grade Package Pins -5 Lead-Free PQFP ...
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... LFXP2-5E-6M132C LFXP2-5E-7M132C LFXP2-5E-5FT256C LFXP2-5E-6FT256C LFXP2-5E-7FT256C Part Number LFXP2-8E-5M132C LFXP2-8E-6M132C LFXP2-8E-7M132C LFXP2-8E-5FT256C LFXP2-8E-6FT256C LFXP2-8E-7FT256C Part Number LFXP2-17E-5FT256C LFXP2-17E-6FT256C LFXP2-17E-7FT256C LFXP2-17E-5F484C LFXP2-17E-6F484C LFXP2-17E-7F484C Part Number LFXP2-30E-5FT256C LFXP2-30E-6FT256C LFXP2-30E-7FT256C LFXP2-30E-5F484C LFXP2-30E-6F484C LFXP2-30E-7F484C LFXP2-30E-5F672C LFXP2-30E-6F672C LFXP2-30E-7F672C Commercial Voltage Grade Package 1.2V -5 csBGA 1.2V -6 csBGA 1.2V ...
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... Part Number LFXP2-40E-5F484C LFXP2-40E-6F484C LFXP2-40E-7F484C LFXP2-40E-5F672C LFXP2-40E-6F672C LFXP2-40E-7F672C Part Number LFXP2-5E-5M132I LFXP2-5E-6M132I LFXP2-5E-6FT256I Part Number LFXP2-8E-5M132I LFXP2-8E-6M132I LFXP2-5E-5FT256I LFXP2-8E-5FT256I LFXP2-8E-6FT256I Part Number LFXP2-17E-5FT256I LFXP2-17E-6FT256I LFXP2-17E-5F484I LFXP2-17E-6F484I Part Number LFXP2-30E-5FT256I LFXP2-30E-6FT256I LFXP2-30E-5F484I LFXP2-30E-6F484I LFXP2-30E-5F672I LFXP2-30E-6F672I Voltage Grade Package 1.2V -5 fpBGA 1.2V -6 fpBGA 1.2V -7 fpBGA 1 ...
Page 100
... Lattice Semiconductor Part Number LFXP2-40E-5F484I LFXP2-40E-6F484I LFXP2-40E-5F672I LFXP2-40E-6F672I Voltage Grade Package 1.2V -5 fpBGA 1.2V -6 fpBGA 1.2V -5 fpBGA 1.2V -6 fpBGA 5-7 Ordering Information LatticeXP2 Family Data Sheet Pins Temp. LUTs (k) 484 IND 40 484 IND 40 672 IND 40 672 IND 40 ...
Page 101
... PCI: www.pcisig.com © 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
Page 102
... DC and Switching Characteristics © 2011 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
Page 103
... Removed XP2-17 “8W” OPNs. Recommended Operating Conditions table, added footnote 5. On-Chip Flash Memory Specifications table, added footnote 1. BLVDS DC Conditions, corrected column title ohms. sysCONFIG Port Timing Specifications table, added footnote 1 for DINIT 7-2 Revision History LatticeXP2 Family Data Sheet Change Summary ...
Page 104
... Section II. LatticeXP2 Family Technical Notes ...
Page 105
... SSTL3 Class I, II © 2009 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
Page 106
... SSTL18 Class II Differential Interfaces Differential SSTL3, Class I, II Differential SSTL2, Class I Differential SSTL2, Class II Differential SSTL18, Class I Differential SSTL18, Class II Differential HSTL18, Class I Differential HSTL18, Class II Differential HSTL15, Class I LatticeXP2 sysIO Usage Guide V (Nom.) REF 1.25 0.9 — — — — ...
Page 107
... RSDS 1. Emulated with external resistors. 2. PCI33 is PCIX compatible. sysIO Banking Scheme LatticeXP2 devices have eight general purpose programmable sysIO banks. Each of the eight general purpose sysIO banks has a V supply voltage, and two reference voltages, V CCIO general purpose banks. On the top and bottom banks, the sysIO buffer pair consists of two single-ended output drivers and two sets of sin- gle-ended input buffers (both ratioed and referenced) ...
Page 108
... Therefore, only SSTL25_II signaling is allowed. For DDR2 memory interfaces REF1 this should be connected to 0.9V, and only SSTL18_II signaling is allowed. Mixed Voltage Support in a Bank The LatticeXP2 sysIO buffer is connected to three parallel ratioed input buffers. These three parallel buffers are connected and V ...
Page 109
... Differential All Single-ended, All Single-ended, Differential Differential PCI33 without clamp PCI33 with clamp 2 LVDS (3.5mA) Buffers 8-5 LatticeXP2 sysIO Usage Guide . This option only takes CCIO . Table 8-4 shows the sysIO stan- CCIO Output sysIO Standards 1.5V 1.8V 2.5V Yes Yes ...
Page 110
... This allows a pair of single-ended drivers to be used to drive complementary outputs with the lowest possible skew between the signals. This is used for driv- ing complementary SSTL and HSTL signals (as required by the differential SSTL and HSTL clock inputs on syn- LatticeXP2 sysIO Usage Guide Programmable Drive (mA ...
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... Appendices A, B and C list examples of how these can be assigned using each of these methods. This section describes each of these attributes in detail. IO_TYPE This is used to set the sysIO standard for an I/O. The V the attribute names itself. There is no separate attribute to set the V I/O types. LatticeXP2 sysIO Usage Guide Programmable Drive (mA 16, 20 ...
Page 112
... LVCMOS and LVTTL I/O standards can be set to open drain configuration by using the OPENDRAIN attribute. Values: ON, OFF Default: OFF DRIVE The DRIVE attribute will set the programmable drive strength for the output standards that have programmable drive capability LatticeXP2 sysIO Usage Guide IO_TYPE LVCMOS25 LVDS25 1 RSDS ...
Page 113
... This allows a designer to specify slew rate control on a pin-by-pin basis. Values: FAST, SLOW Default: FAST DRIVE ( 12, 16 12, 16 12, 16, 20 PULL Options PULLMODE Value UP DOWN KEEPER NONE Input Type PCICLAMP Value ON (default), OFF OFF (default), ON OFF (default), ON 8-9 LatticeXP2 sysIO Usage Guide Default (mA ...
Page 114
... Design Planner in the ispLEVER software. The appendices explain this in further detail. Design Considerations and Usage This section discusses some of the design rules and considerations that must be taken into account when design- ing with the LatticeXP2 sysIO buffer Banking Rules • for any bank is set to 3 ...
Page 115
... Lattice Semiconductor Differential I/O Implementation The LatticeXP2 devices support a variety of differential standards as detailed in the following sections. LVDS True LVDS (LVDS25) drivers are available on 50% of the I/Os on the left and right side of the devices. LVDS input support is provided on all sides of the device. All four sides of the device support LVDS using complementary LVC- MOS drivers with external resistors (LVDS25E) ...
Page 116
... DIN of Pinname: signal is “ ”; attribute DOUT: string; attribute DOUT of Pinname: signal is “ ”; attribute LOC: string; attribute LOC of Pinname: signal is “pin_locations”; SIGNAL IS “PCI33”; SIGNAL IS “LVCMOS33”; SIGNAL IS “LVDS25”; 8-12 LatticeXP2 sysIO Usage Guide ® RTL Synthesis ...
Page 117
... ATTRIBUTE din OF input_vector: SIGNAL IS “ “; ATTRIBUTE dout OF output_vector: SIGNAL IS “ “; LOC --***Attribute Declaration*** ATTRIBUTE LOC : string; --*** LOC assignment for I/O Pin*** ATTRIBUTE LOC OF input_vector: SIGNAL IS “E3,B3,C3 “; LatticeXP2 sysIO Usage Guide SIGNAL IS “DOWN”; SIGNAL IS “UP”; SIGNAL IS “ON”; 8-13 ...
Page 118
... PinType PinName /* synthesis PCICLAMP =” PCIClamp Value”*/; PinType PinName /* synthesis SLEWRATE=”Slewrate Value”*/; PinType PinName /* synthesis FIXEDDELAY=”Fixeddelay Value”*/; PinType PinName /* synthesis DIN=” “*/; PinType PinName /* synthesis DOUT=” “*/; PinType PinName /* synthesis LOC=”pin_locations “*/; 8-14 LatticeXP2 sysIO Usage Guide ...
Page 119
... PinName OPENDRAIN OpenDrain Value // pragma attribute PinName DRIVE Drive Value // pragma attribute PinName IO_TYPE Pullmode Value // pragma attribute PinName PCICLAMP PCIClamp Value // pragma attribute PinName IO_TYPE Slewrate Value // pragma attribute PinName IO_TYPE Fixeddelay Value // pragma attribute PinName LOC pin_location 8-15 LatticeXP2 sysIO Usage Guide ...
Page 120
... Figures 8-2 and 8-3 show the Pin Attribute sheet and the Cell Attribute sheet views of the preference editor. For fur- ther information on how to use the Preference Editor, refer to the ispLEVER Help documentation in the Help menu option of the software. Figure 8-2. Port Attributes Tab Figure 8-3. Cell Attributes Tab LatticeXP2 sysIO Usage Guide 8-16 ...
Page 121
... This command places the port Clk0 on the site A4: LOCATE COMP “Clk0” SITE “A4”; This command places the component PFU1 on the site named R1C7: LOCATE COMP “PFU1” SITE “R1C7”; LOCATE VREF “ref1” SITE PR29C; LatticeXP2 sysIO Usage Guide 8-17 ...
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... Syntax LOCATE VREF <vref_name> SITE <site_name>; Example IOBUF GROUP <group_name> BANK=<bank_name> VREF=<Vref_name> LOCATE VREF “ref1” SITE PR29C; LOCATE VREF “ref2” SITE PR48B; IOBUF GROUP "group1" IO_TYPE=SSTL18_II BANK=0 VREF=vref1 ; LatticeXP2 sysIO Usage Guide 8-18 pin within a bank. REF ...
Page 123
... LatticeXP2 Top Level View Figure 9-1 provides a view of the primary clocking structure of the LatticeXP2-40 device. Figure 9-1. LatticeXP2 Clocking Structure (LFXP2-40) © 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
Page 124
... Number of regions Edge Clocks The LatticeXP2 device has two Edge Clocks (ECLK) per side. These clocks, which have low injection time and skew, are used to clock I/O registers. Edge clock resources are designed for high speed I/O interfaces with high fanout capability. Refer to Appendix B for detailed information on ECLK locations and connectivity. ...
Page 125
... Lattice Semiconductor Figure 9-2 describes the structure of the secondary clocks and edge clocks. Figure 9-2. LatticeXP2 Secondary Clocks and Edge Clocks (LFXP2-40) Primary Clock Note The CLKOP must be used as the feedback source to optimize PLL performance. Most designers use PLLs for clock tree injection removal mode and the CLKOP should be assigned to a primary clock ...
Page 126
... Refer to Appendix A for detailed clock network diagrams. sysCLOCK™ PLL The LatticeXP2 PLL provides features such as clock injection delay removal, frequency synthesis, phase/duty cycle adjustment, and dynamic delay adjustment. Figure 9-4 shows the block diagram of the LatticeXP2 PLL. Figure 9-4. LatticeXP2 PLL Block Diagram WRDEL ...
Page 127
... Duty Trim Adjustment With the LatticeXP2 device family, the duty cycle can be fine-tuned with the Duty Trim Adjustment. Fine Delay Adjust This optional feature is controlled by the input port, WRDEL. See information on the WRDEL input in the next sec- tion of this document ...
Page 128
... RSTK is the reset input for the K-Divider. This K-Divider reset is used to synchronize the K-Divider output clock to the input clock. LatticeXP2 has an optional gearbox in the I/O cell for both outputs and inputs. The K-Divider reset is useful for the gearbox implementation. RSTK is active high. ...
Page 129
... These dividers determine the output frequencies of each output clock. The user is not allowed to input an invalid combination. Valid combinations are determined by the input frequency, the dividers, and the PLL specifications. Note: Unlike PLLs in the LatticeECP™, LatticeEC™, LatticeXP™ and MachXO™ devices, the CLKOP divider val- ues are the same whether or not CLKOS is used. ...
Page 130
... Figure 9-6. LatticeXP2 PLL Primitive Symbol EPLLD Design Migration from LatticeECP2 to LatticeXP2 The EPLLD generated for LatticeECP2 can be used with minor changes. If the configuration does not include Dynamic Phase and Duty Options, the migration is fully supported. If Dynamic Phase and Duty Options are included, the user must tie the DPAMODE port to ground ...
Page 131
... DPHASE[3:0] Phase (°) 0000 0 0001 22.5 0010 45 0011 67.5 0100 90 0101 112.5 0110 135 0111 157.5 1000 180 1001 202.5 1010 225 1011 247.5 1100 270 1101 292.5 1110 315 1111 337.5 9-9 LatticeXP2 sysCLOCK PLL Design and Usage Guide PLL ...
Page 132
... Figure 9-8 shows the main window when PLL is selected. The only entry required in this window is the module name. Other entries are set to the project settings. Users may change these entries, if desired. After entering the module name of choice, clicking on Customize will open the Configuration Tab window as shown in Figure 9. LatticeXP2 sysCLOCK PLL Duty Cycle (1/16th of a Period) ...
Page 133
... Divider value to maximize the f VCO tings are set, clicking the Calculate button will display the frequencies. Figure 9-9 shows the Configuration Tab. and achieve optimum PLL performance. After input frequency and divider set- 9-11 LatticeXP2 sysCLOCK PLL Design and Usage Guide ...
Page 134
... Lattice Semiconductor Figure 9-9. LatticeXP2 PLL Configuration Tab Table 9-7 describes the user parameters in the IPexpress GUI and their usage. Table 9-7. User Parameters in the IPexpress GUI User Parameters Frequency Mode Divider Mode Frequency CLKI Divider Feedback Mode CLKFB Divider None Static Mode PLL Phase & ...
Page 135
... Actual frequency achievable. Read only Enable CLKOK2 output clock Provide PLL Reset Port (RESET) Provide CLKOK Reset Port (RSTK) Provide CLKOS Fine Delay Port (WRDEL) Import .lpc file to ispLEVER project 9-13 LatticeXP2 sysCLOCK PLL Design and Usage Guide Range Default ON/OFF OFF 10 MHz to ...
Page 136
... PLL. CLKI CLKOP PLL CLKFB CLKI Clock Injection Delay Clock at Clock Tree without PLL CLKOP/CLKOS at Clock Tree with PLL CLKOP PLL CLKOS 9-14 LatticeXP2 sysCLOCK PLL Design and Usage Guide Clock Tree ...
Page 137
... FPGA clocks for shift registers (x2, x4, x8) and DDR/SPI4 I/O logic interfaces. CLKDIV Primitive Definition Users can instantiate CLKDIV in the source code as defined in this section. Figure 9-13 and Tables 9-8 and 9-9 describe the CLKDIVB definitions. Figure 9-13. CLKDIV Primitive Symbol LatticeXP2 sysCLOCK PLL CLKDIVB CDIV1 CLKI RST ...
Page 138
... Reset Input, asynchronously forces all outputs low. Releases outputs synchronously to input clock. Divided BY 1 Output Divided BY 2 Output Divided BY 4 Output Divided BY 8 Output Description Value GSR Enable ENABLED/DISABLED std_logic; std_logic); 9-16 LatticeXP2 sysCLOCK PLL Design and Usage Guide Default DISABLED ...
Page 139
... Mux/DeMux gearing. The second circuit shows that a DLL can replace CLKDIV for x2 and x4 applications. Figure 9-14. CLKDIV Application Example Data 8 GEARING D Q (2x) Primary ECLK CLKDIV RST 9-17 LatticeXP2 sysCLOCK PLL Design and Usage Guide 16 Clock ...
Page 140
... Figure 9-16. CLKDIV Release Behavior CLKI RST CDIV1 RELEASE CDIV2 CDIV4 CDIV8 De-asserted RST registered After de-asserted RST is registered all outputs start toggling. De-asserted RST is registered. Release synchronizes Clock start counting outputs 9-18 LatticeXP2 sysCLOCK PLL Design and Usage Guide ...
Page 141
... Table 9-10 defines the I/O ports of the DCS block. There are eight modes to select from. Table 9-11 describes how each mode is configured. Table 9-10. DCS I/O Definition I/O Input Output DCS CLK0 CLK1 DCSOUT SEL Name Description SEL Input Clock Select CLK0 Clock input 0 CLK1 Clock Input 1 DCSOUT Clock Output 9-19 LatticeXP2 sysCLOCK PLL Design and Usage Guide ...
Page 142
... DCSOUT SEL Falling edge: - Wait for CLK1 falling edge, latch output & remain low - Switch output at CLK0 falling edge Description DCS MODE = POS DCS MODE = NEG 9-20 LatticeXP2 sysCLOCK PLL Design and Usage Guide Output SEL=0 SEL=1 CLK0 CLK1 CLK0 CLK1 ...
Page 143
... END COMPONENT; attribute DCSMODE : string; attribute DCSMODE of DCSinst0 : label is “POS”; begin DCSInst0: DCS -- synthesis translate_off GENERIC MAP ( LatticeXP2 sysCLOCK PLL Design and Usage Guide DCS MODE = LOW_LOW CLK0 SEL DCSOUT - Switch low @CLK0 falling edge SEL is high, output stays low at on CLK0 rising edge ...
Page 144
... Oscillator (OSCE) There is a dedicated oscillator in the LatticeXP2 device whose output is made available for users. The oscillator frequency output is routed through a divider which is used as an input clock to the clock tree. The available outputs of the divider are shown in Table 9-13. The oscillator frequency output can be further divided by internal logic (user logic) for lower frequencies, if desired ...
Page 145
... Hotline: 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: techsupport@latticesemi.com Internet: www.latticesemi.com Revision History Date February 2007 February 2010 Version 01.0 Initial release. 01.1 Reconciled LOCK description among MachXO, LatticeXP2, LatticeECP2/M and LatticeECP3. 9-23 LatticeXP2 sysCLOCK PLL Design and Usage Guide Change Summary ...
Page 146
... Lattice Semiconductor Appendix A. Primary Clock Sources and Distribution Figure 9-22. LatticeXP2 Primary Clock Sources and Distribution CLK0 CLK1 CLK2 CLK3 CLK4 CLK5 General Routing 2 36:1 36:1 PCLKT7 CLKOP CLKOS GPLL* CLKOK CLKOK2 CLKOP CLKOS GPLL CLKOK CLKOK2 CLKDIV1 CLKDIV2 CLKDIV CLKDIV4 ...
Page 147
... Figure 9-24. PLL, CLKDIV and ECLK Locations and Connectivity PCLKT7 Internal Node CLKOP ULGPLL CLKOS ULGPLL_IN LLGPLL_IN CLKOP LLGPLL CLKOS Internal Node PCLKT6 LatticeXP2 sysCLOCK PLL Design and Usage Guide ECLK1 ECLK2 ECLK2 ECLK1 9-25 PCLKT2 Internal Node CLKOP URGPLL CLKOS URGPLL_IN ...
Page 148
... USE PRIMARY NET clk_fast; USE PRIMARY DCS NET “bf_clk”; USE PRIMARY PURE NET “bf_clk” QUADRANT_TL; USE SECONDARY Use a secondary clock resource to route the specified net: USE SECONDARY NET “clk_lessfast” QUADRANT_TL; LatticeXP2 sysCLOCK PLL Design and Usage Guide 9-26 ...
Page 149
... PLL_PHASE_BACK preference works as if negative phase adjustment is available. Site Resource ULPPLL.MCLK to R3C14.CLK0 pll_rxclk Site Resource D5.PAD to D5.INCK RxClk D5.INCK to ULPPLL.CLKIN RxClk_c ULPPLL.CLKIN to ULPPLL.MCLK pll_inst/pll_utp_0_0 ULPPLL.MCLK to R3C14.CLK0 pll_rxclk 2.000000 ns HOLD 1.000000 9-27 LatticeXP2 sysCLOCK PLL Design and Usage Guide ns CLKPORT “clk” ...
Page 150
... The Pre-Map Preference Editor can be used to set the PLL_PHASE_BACK attribute. 1. Open the Design Planner (Pre-Map the Design Planner control window, select View -> Spreadsheet View the Spreadsheet View window, select Input_setup/Clock_to_out... The INPUT_SETUP/CLOCK_TO_OUT Preference window is shown in Figure 9-25. Figure 9-25. INPUT_SETUP/CLOCK_TO_OUT Preference Window LatticeXP2 sysCLOCK PLL Design and Usage Guide 9-28 ...
Page 151
... Total Memory Bits © 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
Page 152
... Lattice Semiconductor Figure 10-1. Simplified Block Diagram, LatticeXP2 Device (Top Level) On-chip Oscillator Programmable Function Units (PFUs) SPI Port sysMEM Block RAM DSP Blocks sysCLOCK PLLs Utilizing IPexpress Designers can utilize IPexpress to easily specify a variety of memories in their designs. These modules are con- structed using one or more memory primitives along with general purpose routing and LUTs, as required ...
Page 153
... IPexpress Flow For generating any of these memories, create (or open) a project for the LatticeXP2 devices. From the Project Navigator, select Tools > IPexpress or click on the button in the toolbar when LatticeXP2 devices are targeted in the project. This opens the IPexpress main window as shown in Figure 10-2. ...
Page 154
... VHDL”, and “Schematic/ Verilog-HDL” if the project type is Verilog- HDL. The Device pull-down menu allows users to select different devices within the same family, LatticeXP2 in this example. By clicking the Customize button, another window opens where users can customize the RAM (Figure 10-4) ...
Page 155
... This file is generated along with the module. Users can click on the Load Parameters but- ton to load the parameters of a previously generated module to re-visit or make changes to them. Once the module is generated, users can either instantiate the *.lpc or the Verilog-HDL/ VHDL file in top-level mod- ule of their design. LatticeXP2 Memory Usage Guide 10-5 ...
Page 156
... When Error[1]=1, it indicates that there was a 2-bit error which cannot be corrected. Single Port RAM (RAM_DQ) – EBR Based The EBR blocks in LatticeXP2 devices can be configured as Single Port RAM or RAM_DQ. IPexpress allows users to generate the Verilog-HDL or VHDL along EDIF netlist for the memory size as per design requirements. ...
Page 157
... PFU (external to the EBR blocks). Each EBR block consists of 18,432 bits of RAM. The values for x (address) and y (data) for each EBR block for the devices are listed in Table 10-3. Table 10-3. Single Port Memory Sizes for 16K Memories for LatticeXP2 Single Port Memory Size ...
Page 158
... Lattice Semiconductor Table 10-4. Single Port RAM Attributes for LatticeXP2 Attribute Address depth Address Depth Read Port Data Width Data Word Width Read Port Register Mode (Pipelining) Enable Output Registers for Write Port Enable GSR Enables Global Set Reset Reset Mode ...
Page 159
... SUADDR_EBR Address Add_0 Data Data_0 t SUDATA_EBR Q t HWREN_EBR t HADDR_EBR Add_1 Add_0 Data_1 t HDATA_EBR Invalid Data t HWREN_EBR t HADDR_EBR Add_1 Add_0 Data_1 t HDATA_EBR Invalid Data 10-9 LatticeXP2 Memory Usage Guide t HCE_EBR Add_1 Add_2 Data_0 Data_1 Data_2 t CO_EBR t HCE_EBR Add_1 Add_2 Data_0 Data_1 t COO_EBR ...
Page 160
... Invalid Data t t SUWREN_EBR HWREN_EBR t HADDR_EBR Add_1 Data_1 Data_2 t HDATA_EBR Data_0 Data_1 t CO_EBR t t SUWREN_EBR HWREN_EBR t HADDR_EBR Add_1 Data_1 Data_2 t HDATA_EBR Data_0 10-10 LatticeXP2 Memory Usage Guide t HCE_EBR Add_0 Data_3 Data_4 Data_2 Data_3 Data_4 t HCE_EBR Add_0 Data_3 Data_4 Data_1 Data_2 Data_3 t COO_EBR ...
Page 161
... Lattice Semiconductor True Dual Port RAM (RAM_DP_TRUE) – EBR Based The EBR blocks in the LatticeXP2 devices can be configured as True-Dual Port RAM or RAM_DP_TRUE. IPex- press allows users to generate the Verilog-HDL, VHDL or EDIF netlists for the memory size as per design require- ments. IPexpress generates the memory module as shown in Figure 10-10. ...
Page 162
... Each EBR block consists of 18,432 bits of RAM. The values for x’s (for address) and y’s (data) for each EBR block for the devices are listed in Table 10-6. Table 10-6. True Dual Port Memory Sizes for 16K Memory for LatticeXP2 Dual Port ...
Page 163
... Add_B0 AddressB Data_B0 DataB t SUDATA_EBR QB t HWREN_EBR t HADDR_EBR Add_A1 Add_A0 Data_A1 t HDATA_EBR Invalid Data t HWREN_EBR t HADDR_EBR Add_B1 Add_B0 Data_B1 t HDATA_EBR Invalid Data 10-13 LatticeXP2 Memory Usage Guide t HCE_EBR Add_A1 Add_A2 Data_A0 Data_A1 Data_A2 t CO_EBR t HCE_EBR Add_B1 Add_B2 Data_B0 Data_B1 Data_B2 t CO_EBR ...
Page 164
... WrEnB t SUADDR_EBR AddressB Add_B0 Data_B0 DataB t SUDATA_EBR QB t HWREN_EBR t HADDR_EBR Add_A1 Add_A0 Data_A1 t HDATA_EBR Invalid Data t HWREN_EBR t HADDR_EBR Add_B1 Add_B0 Data_B1 t HDATA_EBR Invalid Data 10-14 LatticeXP2 Memory Usage Guide t HCE_EBR Add_A1 Add_A2 Data_A0 Data_A1 t COO_EBR t HCE_EBR Add_B1 Add_B2 Data_B0 Data_B1 t COO_EBR ...
Page 165
... Invalid Data t SUWREN_EBR t HWREN_EBR t HADDR_EBR Add_A1 Data_A1 Data_A2 t HDATA_EBR Data_A0 Data_A1 t CO_EBR t SUWREN_EBR t HWREN_EBR t HADDR_EBR Add_B1 Data_B1 Data_B2 t HDATA_EBR Data_B0 Data_B1 t CO_EBR 10-15 LatticeXP2 Memory Usage Guide t HCE_EBR Add_A0 Data_A3 Data_A4 Data_A2 Data_A3 Data_A4 t HCE_EBR Add_B0 Data_B3 Data_B4 Data_B2 Data_B3 Data_B4 ...
Page 166
... Invalid Data t t SUWREN_EBR HWREN_EBR t HADDR_EBR Add_1 Data_1 Data_2 t HDATA_EBR Data_0 t t SUWREN_EBR HWREN_EBR t HADDR_EBR Add_1 Data_1 Data_2 t HDATA_EBR Data_0 10-16 LatticeXP2 Memory Usage Guide t HCE_EBR Add_0 Data_3 Data_4 Data_1 Data_2 Data_3 t COO_EBR t HCE_EBR Add_0 Data_3 Data_4 Data_1 Data_2 Data_3 t COO_EBR ...
Page 167
... Lattice Semiconductor Pseudo Dual Port RAM (RAM_DP) – EBR Based The EBR blocks in LatticeXP2 devices can be configured as Pseudo-Dual Port RAM or RAM_DP. IPexpress allows users to generate the Verilog-HDL or VHDL along with EDIF netlists for the memory size as per design require- ments. IPexpress generates the memory module as shown in Figure 10-15. ...
Page 168
... Each EBR block consists of 18,432 bits of RAM. The values for x’s (for address) and y’s (data) for each EBR block for the devices are as in Table 10-9. Table 10-9. Pseudo-Dual Port Memory Sizes for 16K Memory for LatticeXP2 Pseudo-Dual Port Memory ...
Page 169
... Figure 10-16. PSEUDO DUAL PORT RAM Timing Diagram - without Output Registers WrClock t SUCE_EBR WrClockEn RdClock RdClockEn t SUADDR_EBR WrAddress Add_0 t SUADDR_EBR RdAddress Data Data_0 t SUDATA_EBR Q t HCE_EBR t SUCE_EBR t HADDR_EBR Add_1 t HADDR_EBR Add_0 Data_1 t HDATA_EBR Invalid Data 10-19 LatticeXP2 Memory Usage Guide t HCE_EBR Add_2 Add_1 Add_2 Data_2 Data_0 Data_1 t CO_EBR Dat a_2 ...
Page 170
... Q Read Only Memory (ROM) - EBR Based The EBR blocks in the LatticeXP2 devices can be configured as Read Only Memory or ROM. IPexpress allows users to generate the Verilog-HDL or VHDL and the EDIF netlist for the memory size, as per design requirements. Users are required to provide the ROM memory content in the form of an initialization file. ...
Page 171
... Read Only Memory (ROM) with these options. Each EBR block consists of 18,432 bits of RAM. The values for x’s (for address) and y’s (data) for each EBR block for the devices are as per Table 10-12. Table 10-12. ROM Memory Sizes for 16K Memory for LatticeXP2 ROM 16K x 1 ...
Page 172
... Lattice Semiconductor Table 10-13. Pseudo-Dual Port RAM Attributes for LatticeXP2 Attribute Address depth Address Depth Read Port Data Width Data Word Width Read Port Enable Output Registers Register Mode (Pipelining) for Write Port NOREG, OUTREG Enable GSR Enables Global Set Reset ...
Page 173
... Lattice Semiconductor First In First Out (FIFO, FIFO_DC) – EBR Based FIFOs are not supported in certain devices such as the LatticeECP/EC, LatticeECP2/M, LatticeXP and MachXO. The hardware has Embedded Block RAM (EBR) which can be configured in Single Port (RAM_DQ), Pseudo-Dual Port (RAM_DP) and True Dual Port (RAM_DP_TRUE) RAMs. The FIFOs in these devices can be emulated FIFOs that are built around these RAMs ...
Page 174
... In this case, the Almost Full flag is in the 2 location before the FIFO is filled. The Almost Full flag is asserted when the N-2 location is written, and the Full flag is asserted when the last word is written into the FIFO. Data_1 Data_2 Data_3 Data_4 Invalid Q Data_N-2 Data_N-1 Data_N Data_X Invalid Q 10-24 LatticeXP2 Memory Usage Guide Data_5 Data_X ...
Page 175
... There is also the extra option for Output registers to be enabled by the RdEn signal. Invalid Data Invalid Data Data_1 Data_2 Data_3 Invalid Data Data_N-4 Data_N-3 Data_N-2 Data_N-1 10-25 LatticeXP2 Memory Usage Guide Data_4 Data_5 Data_N ...
Page 176
... Full Almost Full Figure 10-26. FIFO with Output Registers, End of Data Write Cycle Reset Clock WrEn RdEn Data Q Empty Almost Empty Full Almost Full Data_1 Data_2 Data_3 Data_4 Invalid Q Data_N-2 Data_N-1 Data_N Data_X Invalid Q 10-26 LatticeXP2 Memory Usage Guide Data_5 Data_X ...
Page 177
... FIFO). The RdEn should also be high during that clock cycle, otherwise the data takes an extra clock cycle when the RdEn goes true. Invalid Data Invalid Data Data_1 Data_2 Invalid Data Data_N-5 Data_N-4 Data_N-3 Data_N-2 10-27 LatticeXP2 Memory Usage Guide Data_3 Data_4 Data_N-1 Data_N ...
Page 178
... Thus, when these flags are required to go true, there is no latency. However, due to the design of the flag logic running on two clock domains, there is latency during the de-assertion. Data_1 Data_2 Data_3 Data_4 Invalid Data 10-28 LatticeXP2 Memory Usage Guide Data_5 Data_1 Data_2 ...
Page 179
... Now let us assume that we continue to write into the FIFO_DC to fill it. When the FIFO_DC is filled, the Almost Full and Full Flags are asserted. Figure 10-31 shows the behavior of these flags. In this figure the FIFO_DC depth is 'N'. LatticeXP2 Memory Usage Guide Data_1 Data_2 ...
Page 180
... Now let us look at the waveforms when the contents of the FIFO_DC are read out. Figure 10-32 shows the start of the read cycle. RdEn goes high and the data read starts. The Full and Almost Full flags are de-asserted, as shown. In this case, note that the de-assertion is delayed by two clock cycles. LatticeXP2 Memory Usage Guide Data_N-2 Data_N-1 ...
Page 181
... Figure 10-33. FIFO_DC without Output Registers, End of Data Read Cycle Reset WrClock RdClock RPReset WrEn RdEn Data Q Empty Almost Empty Full Almost Full Invalid Data Data_1 Data_2 Data_3 Data_4 Invalid Data Data_N-3 Data_N-2 Data_N-1 Data_N 10-31 LatticeXP2 Memory Usage Guide Data_5 Data_6 Data_N ...
Page 182
... However only the data out 'Q' that is delayed by one clock cycle. Figure 10-34. FIFO_DC with Output Registers, Start of Data Write Cycle Reset WrClock RdClock RPReset WrEn RdEn Data Invalid Data Q Empty Almost Empty Full Almost Full Data_1 Data_2 Data_3 Data_4 Invalid Q 10-32 LatticeXP2 Memory Usage Guide Data_5 ...
Page 183
... Figure 10-36. FIFO_DC with Output Registers, Start of Data Read Cycle Reset WrClock RdClock RPReset WrEn RdEn Data Q Empty Almost Empty Full Almost Full Data_N-2 Data_N-1 Data_N Invalid Q Invalid Data Invalid Q Data_1 Data_2 Data_3 10-33 LatticeXP2 Memory Usage Guide Invalid Invalid Data Data Data_4 Data_5 ...
Page 184
... Figure 10-38. FIFO_DC with Output Registers and RdEn on Output Registers Reset WrClock RdClock RPReset WrEn RdEn Data Q Empty Almost Empty Full Almost Full Invalid Data Data_N-4 Data_N-3 Data_N-2 Data_1 Invalid Data Invalid Q Data_1 10-34 LatticeXP2 Memory Usage Guide Data_N Data_2 Data_3 ...
Page 185
... Port Name in the PFU Primitive Description CK Clock — Clock Enable — Reset WRE Write Enable AD[3:0] Address DI[1:0] Data In DO[1:0] Data Out 10-35 LatticeXP2 Memory Usage Guide Q Active State Rising Clock Edge Active High Active High Active High — — — ...
Page 186
... ClockEn t SUWREN_PFU WE t SUADDR_PFU Address Add_0 Data Data_0 t SUDATA_PFU Q t HWREN_PFU t HADDR_PFU Add_1 Add_0 Data_1 t HDATA_PFU Data_0 t CORAM_PFU t HWREN_PFU t HADDR_PFU Add_1 Add_0 Data_1 t HDATA_PFU Invalid Data 10-36 LatticeXP2 Memory Usage Guide Add_1 Add_2 Data_1 Data_2 Add_1 Add_2 Data_0 Data_1 Data_2 t CO ...
Page 187
... Read Clock Enable WCK Write Clock — Write Clock Enable WRE Write Enable DI[1:0] Data Input RDO[1:0] Data Out 10-37 LatticeXP2 Memory Usage Guide Q Active State — — Rising Clock Edge Active High Rising Clock Edge Active High Active High — — ...
Page 188
... Figure 10-43. PFU Based Distributed Dual Port RAM Timing Waveform - without Output Registers WrClock t SUCE_EBR WrClockEn WE t SUADDR_EBR WrAddress Add_0 RdAddress Data Data_0 t SUDATA_EBR Q t HCE_EBR t HADDR_EBR Add_1 Add_2 Data_1 Data_2 t HDATA_EBR Invalid Data t CORAM_PFU 10-38 LatticeXP2 Memory Usage Guide Add_0 Add_1 Add_2 Data_0 Data_1 Data_2 ...
Page 189
... The generated module makes use of the 4-input LUT available in the PFU. Additional logic like Clock and Reset is generated by utilizing the resources available in the PFU. t SUCE_PFU t HWREN_PFU t HADDR_PFU Add_1 Add_0 Data_1 t HDATA_PFU Invalid Data Address OutClock PFU-based Distributed ROM OutClockEn Reset 10-39 LatticeXP2 Memory Usage Guide t HWREN_PFU Add_1 Data_0 Data_1 t CORAM_PFU Q t HCE_PFU ...
Page 190
... Out Clock Enable — Reset DO Data Out t HADDR_PFU Add_0 Add_1 Invalid Data Data_0 t CORAM_PFU t HADDR_PFU Add_0 Add_1 Invalid Data 10-40 LatticeXP2 Memory Usage Guide Active State — Rising Clock Edge Active High Active High — Add_2 Data_1 Data_2 Add_2 Data_0 Data_1 CORAM_PFU ...
Page 191
... SPI Flash. Both SPI bus operation modes 0 (0,0) and 3 (1,1) are supported. Figure 10-48. SSPIA Primitive Table 10-17. User TAG Memory Signal Description Basic Specifications for TAG Memory There is one full page of TAG memory in each LatticeXP2 device. Page size ranges from 56 to 451 bytes. Table 10-18. TAG Memory Density SI SSPIA ...
Page 192
... Parameter 7 8 3-Byte Dummy CSCLK t STSU t STVO t STH HI Bytes 1-3 Data 3µs min. Dummy Out 1ms min., 25ms max. Dummy In 100ms min., 1000ms max. Erase TAG memory Dummy 10-42 LatticeXP2 Memory Usage Guide Min Max Units 25 MHz µs ...
Page 193
... The standalone TAG memory is ideal for use as scratch pad memory for critical data, board serialization, board revision logs and programmed pattern identification. The integration of TAG memory into the LatticeXP2 device family saves chip count and board space. It also can be used to replace obsoleted low-density SPI EEPROM devices. ...
Page 194
... Serial Data Input (SI) pin. The Serial Output (SO) pin is enabled on the falling edge of clock 31 to drive out the first bit of the IDCODE. After 32 bits of the IDCODE are shifted out, additional clocking will cause dummy data to be shifted out on SO. LatticeXP2 Memory Usage Guide Byte 2 Byte 3 ...
Page 195
... Chip Select pin to high, are ignored. After the Chip Select pin is driven from low to high, a minimum of three clocks are required to complete the execution of the command. HI Bits JTAG IDCODE 24 Bits Dummy Optional Extra Clocks 3 Clocks To Initiate And Complete HIGH IMPEDANCE 8 Command Shifting Clocks 10-45 LatticeXP2 Memory Usage Guide HI-Z 31 ...
Page 196
... Consequently, over-filling the data buffer will cause over- flow of the data buffer, resulting in loss of data. Optional Extra Clocks Three Clocks to Initiate And Complete HIGH IMPEDANCE 8 Command Shifting Clocks Optional Extra Clocks Three Clocks To Initiate the Erase Action HIGH IMPEDANCE 8 Command Shifting Clocks 10-46 LatticeXP2 Memory Usage Guide ...
Page 197
... The 20 dummy clocks after the transfer is initiated to before enabling the SO pin are considered delay clocks. Flash Memory Cells Optional Extra Clocks Three Clocks To Initiate The Program Action HIGH IMPEDANCE 8 Command Shifting Clocks 10-47 LatticeXP2 Memory Usage Guide Bit 0 SO Bit 0 Flash Cell 0 ...
Page 198
... Chip Select pin to high and holding the CLK pin low. Clocking while holding the Chip Select pin high is optional. If the maximum programming time or erasure has expired and the status bit still is not set to 1, then erase or pro- gramming has failed. LatticeXP2 Memory Usage Guide Flash Memory Cells Time elapsed must be 5µs ...
Page 199
... Figure 10-60. Device Power-up Waveform VCCmin HI Bits Dummy Chip Select Must Track VCC. Boot Up From The Embedded FLASH. Power Up Timing And Voltage Level 10-49 LatticeXP2 Memory Usage Guide Provide Device Additional Erase Or Programming Time HI Dummy Status Bit TAG Memory Is Fully Accessible. ...
Page 200
... The Initialization File is primarily used for configuring the ROMs. The EBR in RAM mode can optionally use this Ini- tialization File also to preload the memory contents. The TAG memory uses hex or binary non-addressed files. Since SPI, it cannot use the addressed hex file. LatticeXP2 Memory Usage Guide 10-50 ...