LFXP2-5E-5TN144I Lattice, LFXP2-5E-5TN144I Datasheet - Page 152

• Manufacturer Part Number: LFXP2-5E-5TN144I
• Description: FPGA - Field Programmable Gate Array 5K LUTs 100 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-5E-5TN144I

• Number Of Macrocells: 5000
• Number Of Programmable I/os: 100
• Data Ram Size: 169984
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: TQFP-144
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 169984
• Number Of I /o: 100
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 10-1. Simplified Block Diagram, LatticeXP2 Device (Top Level)
Utilizing IPexpress
Designers can utilize IPexpress to easily specify a variety of memories in their designs. These modules are con-
structed using one or more memory primitives along with general purpose routing and LUTs, as required. The
available primitives are:
• Single Port RAM (RAM_DQ) – EBR-based
• Dual PORT RAM (RAM_DP_TRUE) – EBR-based
• Pseudo Dual Port RAM (RAM_DP) – EBR-based
• Read Only Memory (ROM) – EBR-Based
• First In First Out Memory (Dual Clock) (FIFO_DC) – EBR-based
• Distributed Single Port RAM (Distributed_SPRAM) – PFU-based
• Distributed Dual Port RAM (Distributed_DPRAM) – PFU-based
• Distributed ROM (Distributed_ROM) – PFU/PFF-based
• User TAG memory (SSPIA) – TAG-based
Programmable
Function Units
(PFUs)
sysMEM Block
RAM
DSP Blocks
On-chip
Oscillator
SPI Port
sysCLOCK PLLs
10-2
Flexible Routing
sysIO Buffers,
Pre-Engineered Source
Synchronous Support
LatticeXP2 Memory Usage Guide
JTAG Port
Flash