LFXP2-5E-5TN144I Lattice, LFXP2-5E-5TN144I Datasheet - Page 217

• Manufacturer Part Number: LFXP2-5E-5TN144I
• Description: FPGA - Field Programmable Gate Array 5K LUTs 100 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-5E-5TN144I

• Number Of Macrocells: 5000
• Number Of Programmable I/os: 100
• Data Ram Size: 169984
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: TQFP-144
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 169984
• Number Of I /o: 100
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 11-5. ODDRMXA Ports
Figure 11-17 shows the LatticeXP2 Output Register Block configured in the ODDRXMA mode.
Figure 11-17. Output Register Block in ODDRXMA Mode
Figure 11-18 shows the ODDRMXA timing waveform.
CLK
DA
DB
RST
DQSXFER
Q
Notes:
1. RST should be held low during DDR Write operation.
2. DDR output and tristate registers do not have CE support. RST is available for the tristate DDRX mode (while read-
3. When asserting reset during DDR writes, it is important to keep in mind that this only resets the flip-flops and not
ing). The LSR will default to set when used in the tristate mode.
the latches.
Port Name
DQSXFER
ECLK
DB
DA
I/O
I
I
I
I
I
I
System CLK or ECLK
Data at the negative edge of the clock
Data at the positive edge of the clock
Reset
90-degree phase shifted clock coming from the DQSBUFC block
DDR data to the memory
A0
B0
11-13
ODDRXMA
C0
Description
LatticeXP2 High-Speed I/O Interface
Q