LFXP2-5E-5TN144I Lattice, LFXP2-5E-5TN144I Datasheet - Page 210
LFXP2-5E-5TN144I
Manufacturer Part Number
LFXP2-5E-5TN144I
Description
FPGA - Field Programmable Gate Array 5K LUTs 100 I/O Inst on DSP 1.2V -5 Spd
Manufacturer
Lattice
Datasheet
1.LFXP2-8E-5FTN256I.pdf
(341 pages)
Specifications of LFXP2-5E-5TN144I
Number Of Macrocells
5000
Number Of Programmable I/os
100
Data Ram Size
169984
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
TQFP-144
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
169984
Number Of I /o
100
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
*
Operating Temperature
-40°C ~ 100°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP2-5E-5TN144I
Manufacturer:
TI
Quantity:
2 900
Company:
Part Number:
LFXP2-5E-5TN144I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Figure 11-8. DQSBUFC Function
DQS Delay Block: The DQS Delay block receives the digital control delay line (DQSDEL) coming from one of the
two DQSDLL blocks. These control signals are used to delay the DQSI by 90 degrees. DQSO is the delayed DQS
and is connected to the clock input of the first set of DDR registers.
DQS Transition Detect: The DQS Transition Detect block generates the DDR Clock Polarity signal based on the
phase of the FPGA clock at the first DQS transition. The DDR READ control signal and FPGA CLK inputs to this
coming and should be coming from the FPGA core.
DQSXFER: This block generates the 90-degree phase shifted clock to for the DDR Write interface. The input to this
block is the XCLK. The user can choose to connect this either to the edge clock or the FPGA clocks. The
DQSXFER is routed using the DQSXFER tree to all the I/Os spanned by that DQS.
Data Valid Module: The data valid module generates a DATAVALID signal. This signal indicates to the FPGA that
valid data is transmitted out of the input DDR registers to the FPGA core.
Table 11-2 provides a description of the I/O ports associated with the DQSBUFC primitive.
FPGA CLK
READ
XCLK
DQSI
*DV ~ 170mV for DDR1 (SSTL25 signaling)
*DV ~ 120mV for DDR2 (SSTL18 signaling)
Vref- DV*
Vref
+
-
+
-
PRMBDET
11-6
DATA VALID
MODULE
TRANSITION
DQSDEL
DQSXFER
DETECT
DELAY
DQS
DQS
LatticeXP2 High-Speed I/O Interface
DQSXFER
DATAVALID
DQSO
PRMBDET
DDRCLKPOL
DQSC
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