LFXP2-5E-5TN144I Lattice, LFXP2-5E-5TN144I Datasheet - Page 172

• Manufacturer Part Number: LFXP2-5E-5TN144I
• Description: FPGA - Field Programmable Gate Array 5K LUTs 100 I/O Inst on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-5E-5TN144I

• Number Of Macrocells: 5000
• Number Of Programmable I/os: 100
• Data Ram Size: 169984
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: TQFP-144
• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 169984
• Number Of I /o: 100
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 10-13. Pseudo-Dual Port RAM Attributes for LatticeXP2
Figure 10-19. ROM Timing Waveform - without Output Registers
Figure 10-20. ROM Timing Waveform - with Output Registers
Address depth
Data Width
Enable Output Registers Register Mode (Pipelining) for Write Port NOREG, OUTREG
Enable GSR
Reset Mode
Memory File Format
Chip Select Decode
OutClockEn
OutClockEn
OutClock
OutClock
Address
Address
Attribute
Q
Q
t
t
SUADDR_EBR
SUADDR_EBR
t
t
SUCE_EBR
SUCE_EBR
Invalid Data
Address Depth Read Port
Data Word Width Read Port
Enables Global Set Reset
Chip Select Decode for Read Port
Selects the Reset type
Invalid Data
Add_0
Add_0
t
t
Description
HADDR_EBR
HADDR_EBR
Data_0
Add_1
Add_1
10-22
Data_0
Data_1
Add_2
Add_2
16K, 8K, 4K, 2K, 1K,
512
1, 2, 4, 9, 18, 36
ENABLE, DISABLE
BINARY, HEX,
ADDRESSED HEX
0b000, 0b001, 0b010,
0b011, 0b100, 0b101,
0b110, 0b111
ASYNC, SYNC
t
Values
COO_EBR
t
LatticeXP2 Memory Usage Guide
CO_EBR
Data_1
Data_2
Add_3
Add_3
1
NOREG
ENABLE
ASYNC
0b000
Default
Value
Data_2
Data_3
Add_4
Add_4
Through IPexpress
User Selectable
t
t
HCE_EBR
HCE_EBR
YES
YES
YES
YES
YES
YES
Data_3
NO
Data_4