LFXP2-5E-5TN144I Lattice, LFXP2-5E-5TN144I Datasheet - Page 212
LFXP2-5E-5TN144I
Manufacturer Part Number
LFXP2-5E-5TN144I
Description
FPGA - Field Programmable Gate Array 5K LUTs 100 I/O Inst on DSP 1.2V -5 Spd
Manufacturer
Lattice
Datasheet
1.LFXP2-8E-5FTN256I.pdf
(341 pages)
Specifications of LFXP2-5E-5TN144I
Number Of Macrocells
5000
Number Of Programmable I/os
100
Data Ram Size
169984
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
TQFP-144
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
169984
Number Of I /o
100
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
*
Operating Temperature
-40°C ~ 100°C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP2-5E-5TN144I
Manufacturer:
TI
Quantity:
2 900
Company:
Part Number:
LFXP2-5E-5TN144I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
IDDRMX1A
This primitive will implement the input register block in memory mode. The DDR registers are designed to use edge
clock routing on the I/O side and the primary clock on the FPGA side. The ECLK input is used to connect to the
DQS strobe coming from the DQS delay block (DQSBUFC primitive). The SCLK input is connected to the system
(FPGA) clock. DDRCLKPOL is an input from the DQS Clock Polarity tree. This signal is generated by the DQS
Transition detect circuit in the hardware. The DDRCLKPOL signal is used to choose the polarity of the SCLK to the
synchronization registers.
Figure 11-10. IDDRMX1A Symbol
Table 11-3 provides a description of all I/O ports associated with the IDDRMX1A primitive.
Table 11-3. IDDRMX1A Ports
Figure 11-11 shows the Input Register Block configured in the IDDRMX1A mode.
D
ECLK
RST
SCLK
CE
DDRCLKPOL
QA
QB
Note:
DQSBUFC.
Port Name
The DDRCLKPOL input to IDDRMX1A should be connected to the DDRCLKPOL output of
I/O
O
O
I
I
I
I
I
I
DDR Data
Reset
System CLK
Clock enable
DDR clock polarity signal
Data at Positive edge of the CLK
Data at the negative edge of the CLK
The phase shifted DQS should be connected to this input
ECLK
RST
SCLK
CE
DDRCLKPOL
D
IDDRMX1A
11-8
QA
QB
Definition
LatticeXP2 High-Speed I/O Interface
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