LFXP3E-4TN100I Lattice, LFXP3E-4TN100I Datasheet - Page 194

• Manufacturer Part Number: LFXP3E-4TN100I
• Description: IC FPGA 3.1KLUTS 62I/O 100-TQFP
• Manufacturer: Lattice

Specifications of LFXP3E-4TN100I

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 9-11. EBR-based FIFO and FIFO_DC Memory Port Definitions
Reset (or RST) only resets the output registers of the FIFO and FIFO_DC. It does not reset the contents of the
memory.
The various supported sizes for the FIFO and FIFO_DC in LatticeECP/EC and LatticeXP devices are shown in
Table 9-12.
Table 9-12. FIFO and FIFO_DC Data Widths Sizes for LatticeECP/EC and LatticeXP Devices
FIFO Flags
The FIFO and FIFO_DC have four flags available: Empty, Almost Empty, Almost Full and Full. The Almost Empty
and Almost Full flags have a programmable range.
The program ranges for the four FIFO flags are specified in Table 9-13.
Table 9-13. FIFO Flag Settings
The only restriction on the flag setting is that the values must be in a specific order (Empty=0, Almost Empty next,
followed by Almost Full and Full, respectively). The value of Empty is not equal to the value of Almost Empty (or
Full is equal to Almost Full). In this case, a warning is generated and the value of Empty (or Full) is used in place of
Almost Empty (or Almost Full). When coming out of reset, the Active High Flags empty and Almost Empty are set
to high, since they are true.
FIFO Attribute Name
AFF
AEF
Port Name in Generated
FF
EF
Module
CLKW
CLKR
FIFO Size
RST
CLK
512 x 18
256 x 36
WE
DO
RE
FF
AF
EF
AE
DI
8K x 1
4K x 2
2K x 4
1K x 9
Almost empty setting
Almost full setting
Full flag setting
Empty setting
Description
Clock (FIFO)
Read Port Clock (FIFO_DC)
Write Port Clock (FIFO_DC)
Write Enable
Read Enable
Reset
Data Input
Data Output
Full Flag
Almost Full Flag
Empty Flag
Almost Empty
Description
Input Data
DI[17:0]
DI[35:0]
DI[1:0]
DI[3:0]
DI[8:0]
9-29
DI
Programming Range
1 to (FF-1)
1 to (FF-1)
LatticeECP/EC and LatticeXP Devices
2N - 1
0
Rising Clock Edge
Rising Clock Edge
Rising Clock Edge
Active High
Active High
Active High
—
—
Active High
Active High
Active High
Active High
Output Data
DO[17:0]
DO[35:0]
DO[1:0]
DO[3:0]
DO[8:0]
DO
Memory Usage Guide
Program Bits
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