LFXP6C-3TN144I Lattice, LFXP6C-3TN144I Datasheet - Page 337
LFXP6C-3TN144I
Manufacturer Part Number
LFXP6C-3TN144I
Description
IC FPGA 5.8KLUTS 100I/O 144-TQFP
Manufacturer
Lattice
Datasheet
1.LFXP3C-3T100C.pdf
(397 pages)
Specifications of LFXP6C-3TN144I
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP6C-3TN144I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
- Current page: 337 of 397
- Download datasheet (10Mb)
Lattice Semiconductor
Implementing Multiplexers
The flexible configurations of LUTs can realize any 4-, 5-, or 6-input logic function like 2-to-1, 3-to-1 or 4-to-1 multi-
plexers. Larger multiplexers can be efficiently created by programming multiple 4-input LUTs. Synthesis tools camn
automatically infer Lattice FPGA optimized multiplexer library elements based on the behavioral description in the
HDL source code. This provides the flexibility to the Mapper and Place and Route tools to configure the LUT mode
and connections in the most optimum fashion.
Clock Dividers
There are two ways to implement clock dividers in Lattice Semiconductor FPGA devices. The first is to cascade the
registers with asynchronous clocks. The register output feeds the clock pin of the next register (Figure 13-7). Since
the clock number in each PFU is limited to two, any clock divider with more than two bits will require multiple PFU
implementations. As a result, the asynchronous daisy chaining implementation of clock divider will be slower due to
the inter-PFU routing delays. This kind of delays is usually ambiguous and inconsistent because of the nature of
FPGA routing structures.
Figure 13-7. Daisy Chaining of Flip-flops
16:1 MUX
…
process(sel, din)
…
LU
D
begin
end process;
if
elsif (sel="0001") then muxout <= din(1);
elsif (sel="0010") then muxout <= din(2);
elsif (sel="0011") then muxout <= din(3);
elsif (sel="0100") then muxout <= din(4);
elsif (sel="0101") then muxout <= din(5);
elsif (sel="0110") then muxout <= din(6);
elsif (sel="0111") then muxout <= din(7);
elsif (sel="1000") then muxout <= din(8);
elsif (sel="1001") then muxout <= din(9);
elsif (sel="1010") then muxout <= din(10);
elsif (sel="1011") then muxout <= din(11);
elsif (sel="1100") then muxout <= din(12);
elsif (sel="1101") then muxout <= din(13);
elsif (sel="1110") then muxout <= din(14);
elsif (sel="1111") then muxout <= din(15);
else muxout <= '0';
end if;
PFU
(sel="0000") then muxout <= din(0);
13-10
LU
D
PFU
HDL Synthesis Coding Guidelines
for Lattice Semiconductor FPGAs
Related parts for LFXP6C-3TN144I
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
FPGA - Field Programmable Gate Array 5.8K LUTs 142 IO 1.8 /2.5/3.3V -3 Spd I
Manufacturer:
Lattice
Part Number:
Description:
FPGA - Field Programmable Gate Array 5.8K LUTs 188 I/O 1.8/2.5/3.3V -3 Spd
Manufacturer:
Lattice
Datasheet:
Part Number:
Description:
FPGA - Field Programmable Gate Array 5.8K LUTs 100 IO 1.8 /2.5/3.3V -3 Spd I
Manufacturer:
Lattice
Part Number:
Description:
IC FPGA 5.8KLUTS 188I/O 256-BGA
Manufacturer:
Lattice
Datasheet:
Part Number:
Description:
FPGA - Field Programmable Gate Array 5.8K LUTS 142 I/O
Manufacturer:
Lattice
Datasheet:
Part Number:
Description:
FPGA - Field Programmable Gate Array 5.8K LUTs 100 IO 1.8 /2.5/3.3V -4 Spd I
Manufacturer:
Lattice
Datasheet:
Part Number:
Description:
FPGA - Field Programmable Gate Array 5.8K LUTs 142 IO 1.8 /2.5/3.3V -4 Spd
Manufacturer:
Lattice
Datasheet:
Part Number:
Description:
FPGA - Field Programmable Gate Array 5.8K LUTS 100 I/O
Manufacturer:
Lattice
Datasheet:
Part Number:
Description:
FPGA - Field Programmable Gate Array 5.8K LUTs 188 I/O 1.8/2.5/3.3V -4 Spd
Manufacturer:
Lattice
Datasheet:
Part Number:
Description:
FPGA, 1.8V FLASH, INSTANT ON, SMD
Manufacturer:
LATTICE SEMICONDUCTOR
Datasheet:
Part Number:
Description:
FPGA LatticeXP Family 6000 Cells 360MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 256-Pin FBGA Tray
Manufacturer:
LATTICE SEMICONDUCTOR
Datasheet:
Part Number:
Description:
FPGA LatticeXP Family 6000 Cells 400MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 256-Pin FBGA Tray
Manufacturer:
LATTICE SEMICONDUCTOR
Datasheet:
Part Number:
Description:
FPGA LatticeXP Family 6000 Cells 360MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 208-Pin PQFP Tray
Manufacturer:
Lattice
Datasheet: