LFXP15E-3F256I Lattice, LFXP15E-3F256I Datasheet - Page 269
LFXP15E-3F256I
Manufacturer Part Number
LFXP15E-3F256I
Description
IC FPGA 15.5KLUTS 188I/O 256-BGA
Manufacturer
Lattice
Datasheet
1.LFXP3C-3T100C.pdf
(397 pages)
Specifications of LFXP15E-3F256I
Lead Free Status / Rohs Status
Contains lead / RoHS non-compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP15E-3F256I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Figure 11-9. Clock Preferences in the Pre-map Preference Editor
Secondary Clock Sources and Distribution
LatticeECP/EC and LatticeXP devices support quadrant base Secondary Clocks. Figure 11-10 describes the Sec-
ondary Clock arrangement.
Figure 11-10. Secondary Clock Center Switch Box
Limitations on Secondary Clock Availability
As illustrated in Figure 11-11, three secondary clocks are shared with CLK, CE and LSR.
This routing scheme limits the secondary clocks available per quadrant base to three, which results in a maximum
of 12 available secondary clocks per device. Figure 11-11 illustrates the primary and secondary clock distribution
structure of the PFUs.
General
Routing
PCLKT7
4
Scondary Clock Trunk
Scondary Clock Trunk
QUADRANT BL
QUADRANT TR
SCLK0 SCLK1 SCLK2 SCLK3
SCLK0 SCLK1 SCLK2 SCLK3
8:1
8:1
Secondary Clocks in Center Switch Box
8:1
8:1
8:1
8:1
8:1
8:1
11-13
SCLK3 SCLK2 SCLK1 SCLK0
SCLK3 SCLK2 SCLK1 SCLK0
8:1
8:1
Scondary Clock Trunk
Scondary Clock Trunk
sysCLOCK PLL Design and Usage Guide
QUADRANT BR
QUADRANT TR
8:1
8:1
8:1
8:1
8:1
8:1
General
Routing
LatticeECP/EC and LatticeXP
General
Routing
4
4
4
PCLKT2
General
Routing
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