K4M563233G-HN75 Samsung Semiconductor, K4M563233G-HN75 Datasheet - Page 7

• Manufacturer Part Number: K4M563233G-HN75
• Manufacturer: Samsung Semiconductor
• Type: Mobile SDRAMr

Specifications of K4M563233G-HN75

• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 7/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3V
• Package Type: FBGA
• Operating Temp Range: -25C to 85C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2.7V
• Supply Current: 130mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

OPERATING AC PARAMETER
K4M563233G - F(H)N/G/L/F
(AC operating conditions unless otherwise noted)
NOTES:
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
2. Maximum burst refresh cycle : 8
3. Minimum delay is required to complete write.
4. Minimum tRDL=2CLK and tDAL(= tRDL + tRP) is required to complete both of last data write command(tRDL) and precharge command(tRP).
5. All parts allow every cycle column address change.
6. In case of row precharge interrupt, auto precharge and read burst stop.
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
Col. address to col. address delay
Number of valid output data
Number of valid output data
Number of valid output data
and then rounding off to the next higher integer.
Parameter
CAS latency=3
CAS latency=2
CAS latency=1
t
t
t
t
t
t
t
t
t
RAS
RRD
RCD
t
CCD
Symbol
t
RAS
RDL
CDL
DAL
BDL
RC
RP
(min)
(min)
(max)
(min)
(min)
(min)
(min)
(min)
(min)
(min)
(min)
-60
12
18
18
42
60
-
tRDL + tRP
Version
100
-75
15
18
18
45
63
2
1
1
1
2
1
22.5
22.5
67.5
-7L
15
45
0
Mobile-SDRAM
Unit
CLK
CLK
CLK
CLK
ea
ns
ns
ns
ns
us
ns
-
February 2006
Note
1,2
1
1
1
1
3
4
3
3
5
6