ISL54058IRUZ-T Intersil, ISL54058IRUZ-T Datasheet
ISL54058IRUZ-T
Specifications of ISL54058IRUZ-T
Related parts for ISL54058IRUZ-T
ISL54058IRUZ-T Summary of contents
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... Ordering Information PART NUMBER (NOTE) PART MARKING ISL54058IRUZ-T GAC NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb- free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C ...
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Pinouts (Note 1) NOTE: 1. 2.6mmx1.8mmx0.5mm Truth Table ISL54058 ADDA1 ADDA0 ADDB1 ADDB0 NOTE: Logic “0” ...
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... Maximum Junction Temperature (Plastic Package +150°C Maximum Storage Temperature Range -65°C to +150°C Maximum Lead Temperature (Soldering 10s +300°C (Lead Tips Only) Operating Conditions Temperature Range ISL54058IRUZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C Test Conditions +2.7V to +3.3V, GND = 0V, V SUPPLY 8), Unless Otherwise Specified TEST CONDITIONS ...
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Electrical Specifications: 3V Supply PARAMETER POWER SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current 3.3V, V NOTES Input voltage to perform proper function The algebraic convention, whereby the most negative value is ...
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Test Circuits and Waveforms V+ LOGIC 50% INPUT 0V t TRANS VA0, VB0 SWITCH OUTPUT 10 TRANS Logic input waveform is inverted for switches that have the opposite logic sense. FIGURE 1A. ADDRESS t MEASUREMENT POINTS TRANS V+ ...
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Test Circuits and Waveforms V+ C SIGNAL GENERATOR ANALYZER COMx GND R L FIGURE 3. OFF ISOLATION TEST CIRCUIT V+ C SIGNAL GENERATOR Ax ADDX ANALYZER COM B GND R L FIGURE 5. CROSSTALK ...
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If these conditions cannot be guaranteed, then precautions must be implemented to prohibit the current and voltage at the logic pin and signal pins from exceeding the maximum ratings of the switch. The following two methods can be used to ...
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Typical Performance Curves 0 1.65V 0.7 0 1.8V 0 2.7V 0 3.6V 0 (V) COM FIGURE 8. ON RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...
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... L 7. Maximum package warpage is 0.05mm. 8. Maximum allowable burrs is 0.076mm in all directions. 9. JEDEC Reference MO-255. TERMINAL TIP 10. For additional information, to assist with the PCB Land Pattern Design effort, see Intersil Technical Brief TB389. 1.40 0.40 0.20 MILLIMETERS MIN NOMINAL ...