ISL54057IRUZ-T Intersil, ISL54057IRUZ-T Datasheet
ISL54057IRUZ-T
Specifications of ISL54057IRUZ-T
Related parts for ISL54057IRUZ-T
ISL54057IRUZ-T Summary of contents
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... Ordering Information PART NUMBER (NOTE) PART MARKING ISL54057IRUZ-T GAB NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb- free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C ...
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Pinouts (Note 1) NOTE: 1. 2.6mm x 1.8mm x 0.5mm Truth Table ISL54057 INH ADD0 ADD1 NOTE: Logic “0” ≤0.5V. Logic “1” ≥1.4V, with a ...
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... Maximum Junction Temperature (Plastic Package +150°C Maximum Storage Temperature Range -65°C to +150°C Maximum Lead Temperature (Soldering 10s +300°C (Lead Tips Only) Operating Conditions Temperature Range ISL54057IRUZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C Test Conditions +2.7V to +3.3V, GND = 0V, V SUPPLY (Notes 4, 8), Unless Otherwise Specified TEST CONDITIONS ...
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Electrical Specifications: 3V Supply PARAMETER OFF Isolation R = 50Ω (See Figures 3 and 5) Crosstalk, Note 9 POWER SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current 3.3V, V NOTES Input voltage ...
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Test Circuits and Waveforms V+ LOGIC 50% INPUT VA0, VB0 90% SWITCH OUTPUT 0V t OFF Logic input waveform is inverted for switches that have the opposite logic sense. FIGURE 1A. INHIBIT t /t MEASUREMENT POINTS ...
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Test Circuits and Waveforms V+ LOGIC INPUT 0V SWITCH OUTPUT V OUT 0V t BBM FIGURE 2A. t MEASUREMENT POINTS BBM V+ 10nF SIGNAL GENERATOR ANALYZER COMx GND R L Off-Isolation is measured between COM and “Off” ...
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Test Circuits and Waveforms V+ C SIGNAL GENERATOR ADD1 ADD0 Channel Select ANALYZER COM B GND R L Crosstalk is measured between adjacent channels with one channel ON and the other channel OFF. Signal direction ...
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Power-Supply Considerations The ISL54057 construction is typical of most CMOS analog switches, in that they have two supply pins: V+ and GND. V+ and GND drive the internal CMOS switches and set their analog voltage limits. Unlike switches with a ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...
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... L 7. Maximum package warpage is 0.05mm. 8. Maximum allowable burrs is 0.076mm in all directions. 9. JEDEC Reference MO-255. TERMINAL TIP 10. For additional information, to assist with the PCB Land Pattern Design effort, see Intersil Technical Brief TB389. 1.40 0.40 0.20 MILLIMETERS MIN NOMINAL ...