HI3-0509A-5 Intersil, HI3-0509A-5 Datasheet
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HI3-0509A-5
Specifications of HI3-0509A-5
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HI3-0509A-5 Summary of contents
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... Data Acquisition Systems • Industrial Controls • Telemetry CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 1-888-468-3774 Intersil (and design trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003, 2004, 2007. All Rights Reserved FN3143.6 P-P ...
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... HI1-0509A-8 HI1-509A-8 HI3-0509A-5 HI3-509A-5 HI3-0509A-5Z (Note 1) HI3-509A-5Z NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. ...
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Pinouts HI-506A (CERDIP, PDIP) TOP VIEW +V 1 SUPPLY GND 12 V ...
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Truth Tables HI-506A ...
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Functional Diagrams HI-506A OVERVOLTAGE 5V CLAMP AND REF SIGNAL ISOLATION † DIGITAL INPUT PROTECTION V REF HI-508A OVERVOLTAGE 5V CLAMP AND REF ...
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Schematic Diagrams TTL REFERENCE CIRCUIT R10 REF Q4 D3 GND P OVERVOLTAGE P N PROTECTION 200 Ω V- ADD ENABLE 6 HI-506A, HI-507A, HI-508A, HI-509A ADDRESS ...
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Schematic Diagrams (Continued) FROM DECODE OVERVOLTAGE PROTECTION R11 1k IN FROM DECODE 7 HI-506A, HI-507A, HI-508A, HI-509A MULTIPLEX SWITCH OUT P FN3143.6 October 30, 2007 ...
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... Ld PDIP Package . . . . . . . . . . . . . . 16 Ld PDIP Package . . . . . . . . . . . . . . Maximum Junction Temperature CERDIP Packages +175°C PDIP Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Pin = Open; V (Logic Level High) = 4V; V REF AH TEST TEMP ...
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Electrical Specifications Supplies = +15V, -15V; V Unless Otherwise Specified. For Test Conditions, Consult Test Circuits Section. (Continued) PARAMETER Input Leakage Current (High or Low MOS Drive HI-506A/HI-507A AL MOS Drive HI-506A/HI-507A AH ANALOG ...
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Test Circuits and Waveforms 1.4 1.3 +125°C 1.2 1.1 +25°C 1.0 -55°C 0.9 0.8 0.7 0.6 - ANALOG INPUT (V) FIGURE 1B. ON RESISTANCE vs ANALOG INPUT VOLTAGE 100nA 10nA OFF OUTPUT CURRENT ON LEAKAGE ...
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Test Circuits and Waveforms A I S(OFF) ±10V ± 10V FIGURE 2C. I TEST CIRCUIT (NOTE 13) S(OFF) NOTE: 13. Two measurements per channel: ±10V and +10V. (Two measurements per device for I 18 ANALOG INPUT CURRENT ( ...
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Test Circuits and Waveforms ±15V SUPPLY ±10V SUPPLY 10k 100k TOGGLE FREQUENCY (Hz) FIGURE 5A. SUPPLY CURRENT vs TOGGLE FREQUENCY 900 = OPEN FOR LOGIC HIGH LEVEL ≤ ...
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Test Circuits and Waveforms A 3 † HI-506A THRU 50Ω 7/ 8/IN 16 +4.0V EN OUT GND † Similar connection for HI-507A/HI-508A/HI-509A FIGURE 7A. TEST ...
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Test Circuits and Waveforms A 3 † HI-506A THRU OUT GND V A 50Ω † Similar connection for HI-507A//HI-508A/HI-509A FIGURE 8A. TEST ...
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Die Characteristics DIE DIMENSIONS: 159 mils x 83.9 mils METALLIZATION: Type: CuAl ±2k Å Å Thickness: 16k SUBSTRATE POTENTIAL (NOTE): -V SUPPLY PASSIVATION: ±2k Å Å Silox: 12k ±1k Å Å Nitride: 3.5k NOTE: The substrate appears resistive to the ...
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Die Characteristics DIE DIMENSIONS: 108 mils x 83 mils METALLIZATION: Type: CuAl ±2k Å Å Thickness: 16k SUBSTRATE POTENTIAL (NOTE): -V SUPPLY PASSIVATION: ±2k Å Å Silox: 12k ±1k Å Å Nitride: 3.5k NOTE: The substrate appears resistive to the ...
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Ceramic Dual-In-Line Frit Seal Packages (CERDIP) -D- -A- E -B- bbb BASE Q PLANE -C- SEATING PLANE aaa ccc ...
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Dual-In-Line Plastic Packages (PDIP INDEX N/2 AREA -B- -A- D BASE PLANE -C- SEATING PLANE 0.010 (0.25 NOTES: 1. Controlling Dimensions: INCH. In case of conflict between ...
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Ceramic Dual-In-Line Frit Seal Packages (CERDIP) -D- -A- E -B- bbb BASE Q PLANE -C- SEATING PLANE aaa ccc ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...