SAF7118EH/V1/G,518 Trident Microsystems, Inc., SAF7118EH/V1/G,518 Datasheet - Page 158

• Manufacturer Part Number: SAF7118EH/V1/G,518
• Manufacturer: Trident Microsystems, Inc.

Specifications of SAF7118EH/V1/G,518

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NXP Semiconductors
16. Test information
SAF7118_4
Product data sheet
16.1.1 Initialization of boundary scan circuit
16.1.2 Device identification codes
16.1 Boundary scan test
The SAF7118 has built-in logic and 5 dedicated pins to support boundary scan testing
which allows board testing without special hardware (nails). The SAF7118 follows the
“IEEE Std. 1149.1 - Standard Test Access Port and Boundary-Scan Architecture” set by
the Joint Test Action Group (JTAG).
The 5 special pins are Test Mode Select (TMS), Test Clock (TCK), Test Reset (TRST),
Test Data Input (TDI) and Test Data Output (TDO).
The Boundary Scan Test (BST) functions BYPASS, EXTEST, SAMPLE, CLAMP and
IDCODE are all supported; see
found in specification “IEEE Std. 1149.1” . A file containing the detailed Boundary Scan
Description Language (BSDL) description of the SAF7118 is available on request.
Table 148. BST instructions supported by the SAF7118
The Test Access Port (TAP) controller of an IC should be in the reset state
(TEST_LOGIC_RESET) when the IC is in functional mode. This reset state also forces
the instruction register into a functional instruction such as IDCODE or BYPASS.
To solve the power-up reset, the standard specifies that the TAP controller will be forced
asynchronously to the TEST_LOGIC_RESET state by setting the TRST pin LOW.
A device identification register is specified in “IEEE Std. 1149.1b-1994” . It is a 32-bit
register which contains fields for the specification of the IC manufacturer, the IC part
number and the IC version number. Its biggest advantage is the possibility to check for the
correct ICs mounted after production and determination of the version number of ICs
during field service.
Instruction
BYPASS
EXTEST
SAMPLE
CLAMP
IDCODE
Description
This mandatory instruction provides a minimum length serial path (1 bit) between
TDI and TDO when no test operation of the component is required.
This mandatory instruction allows testing of off-chip circuitry and board level
interconnections.
This mandatory instruction can be used to take a sample of the inputs during
normal operation of the component. It can also be used to preload data values into
the latched outputs of the boundary scan register.
This optional instruction is useful for testing when not all ICs have BST. This
instruction addresses the bypass register while the boundary scan register is in
external test mode.
This optional instruction will provide information on the components manufacturer,
part number and version number.
Rev. 04 — 4 July 2008
Multistandard video decoder with adaptive comb filter
Table
148. Details about the JTAG BST-TEST can be
SAF7118
© NXP B.V. 2008. All rights reserved.
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