SAF7118EH/V1/G,518 Trident Microsystems, Inc., SAF7118EH/V1/G,518 Datasheet - Page 173

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SAF7118EH/V1/G,518

Manufacturer Part Number
SAF7118EH/V1/G,518
Description
Manufacturer
Trident Microsystems, Inc.
Datasheet

Specifications of SAF7118EH/V1/G,518

Lead Free Status / Rohs Status
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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SAF7118EH/V1/G,518
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
24. Contents
1
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
3
4
5
6
7
7.1
7.2
8
8.1
8.1.1
8.1.1.1
8.1.1.2
8.1.2
8.1.2.1
8.1.2.2
8.1.2.3
8.1.3
8.1.4
8.1.5
8.2
8.2.1
8.2.2
8.2.3
8.3
8.4
8.4.1
8.4.1.1
8.4.1.2
8.4.1.3
8.4.2
8.4.2.1
SAF7118_4
Product data sheet
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Quick reference data . . . . . . . . . . . . . . . . . . . . . 4
Ordering information . . . . . . . . . . . . . . . . . . . . . 4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pinning information . . . . . . . . . . . . . . . . . . . . . . 6
Functional description . . . . . . . . . . . . . . . . . . 15
Video acquisition/clock . . . . . . . . . . . . . . . . . . . 2
Video decoder. . . . . . . . . . . . . . . . . . . . . . . . . . 2
Component video processing . . . . . . . . . . . . . . 2
Video scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
VBI data decoder and slicer . . . . . . . . . . . . . . . 3
Audio clock generation . . . . . . . . . . . . . . . . . . . 3
Digital I/O interfaces . . . . . . . . . . . . . . . . . . . . . 3
Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7
Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Analog input processing . . . . . . . . . . . . . . . . . 15
Clamping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Gain control . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Chrominance and luminance processing . . . . 20
Chrominance path . . . . . . . . . . . . . . . . . . . . . 21
Luminance path . . . . . . . . . . . . . . . . . . . . . . . 25
Brightness Contrast Saturation (BCS) control
and decoder output levels. . . . . . . . . . . . . . . . 31
Synchronization . . . . . . . . . . . . . . . . . . . . . . . 32
Clock generation circuit . . . . . . . . . . . . . . . . . 32
Power-on reset and CE input . . . . . . . . . . . . . 33
Component video processing . . . . . . . . . . . . . 35
RGB-to-(Y-C
Downformatter . . . . . . . . . . . . . . . . . . . . . . . . 36
Component video BCS control . . . . . . . . . . . . 37
Decoder output formatter . . . . . . . . . . . . . . . . 38
Scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Acquisition control and task handling
(subaddresses 80h, 90h, 91h, 94h to 9Fh
and C4h to CFh) . . . . . . . . . . . . . . . . . . . . . . . 45
Input field processing . . . . . . . . . . . . . . . . . . . 46
Task handling . . . . . . . . . . . . . . . . . . . . . . . . . 47
Output field processing . . . . . . . . . . . . . . . . . . 48
Horizontal scaling . . . . . . . . . . . . . . . . . . . . . . 50
Horizontal prescaler (subaddresses
A0h to A7h and D0h to D7h). . . . . . . . . . . . . . 50
B
-C
R
) matrix . . . . . . . . . . . . . . . . 36
Rev. 04 — 4 July 2008
Multistandard video decoder with adaptive comb filter
8.4.2.2
8.4.3
8.4.3.1
8.4.3.2
8.4.3.3
8.5
8.6
8.6.1
8.6.2
8.6.3
8.6.4
8.6.5
8.7
8.7.1
8.7.2
8.7.3
9
9.1
9.2
9.3
9.4
9.4.1
9.4.1.1
9.4.1.2
9.4.1.3
9.4.1.4
9.4.2
9.4.3
9.5
9.5.1
9.5.2
9.6
9.7
9.8
9.8.1
Input/output interfaces and ports . . . . . . . . . 69
Horizontal fine scaling (variable phase
delay filter; subaddresses A8h to AFh
and D8h to DFh). . . . . . . . . . . . . . . . . . . . . . . 54
Vertical scaling . . . . . . . . . . . . . . . . . . . . . . . . 55
Line FIFO buffer (subaddresses 91h, B4h
and C1h, E4h) . . . . . . . . . . . . . . . . . . . . . . . . 55
Vertical scaler (subaddresses B0h to BFh
and E0h to EFh) . . . . . . . . . . . . . . . . . . . . . . . 56
Use of the vertical phase offsets . . . . . . . . . . 57
VBI data decoder and capture
(subaddresses 40h to 7Fh) . . . . . . . . . . . . . . 60
Image port output formatter
(subaddresses 84h to 87h) . . . . . . . . . . . . . . 61
Scaler output formatter
(subaddresses 93h and C3h). . . . . . . . . . . . . 62
Video FIFO (subaddress 86h) . . . . . . . . . . . . 62
Text FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Video and text arbitration
(subaddress 86h) . . . . . . . . . . . . . . . . . . . . . . 63
Data stream coding and reference signal
generation
(subaddresses 84h, 85h and 93h) . . . . . . . . . 64
Audio clock generation
(subaddresses 30h to 3Fh) . . . . . . . . . . . . . . 66
Master audio clock . . . . . . . . . . . . . . . . . . . . . 67
Signals ASCLK and ALRCLK. . . . . . . . . . . . . 68
Other control signals . . . . . . . . . . . . . . . . . . . 68
Analog terminals . . . . . . . . . . . . . . . . . . . . . . 69
Audio clock signals. . . . . . . . . . . . . . . . . . . . . 70
Clock and real-time synchronization signals . 70
Interrupt handling . . . . . . . . . . . . . . . . . . . . . . 71
Interrupt flags . . . . . . . . . . . . . . . . . . . . . . . . . 71
Power state . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Video decoder . . . . . . . . . . . . . . . . . . . . . . . . 71
VBI data slicer . . . . . . . . . . . . . . . . . . . . . . . . 72
Scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Status reading conditions. . . . . . . . . . . . . . . . 72
Erasing conditions . . . . . . . . . . . . . . . . . . . . . 72
Video expansion port (X port) . . . . . . . . . . . . 72
X port configured as output . . . . . . . . . . . . . . 73
X port configured as input . . . . . . . . . . . . . . . 76
Image port (I port) . . . . . . . . . . . . . . . . . . . . . 76
Host port for 16-bit extension
of video data I/O (H port) . . . . . . . . . . . . . . . . 78
Basic input and output timing diagrams
I port and X port . . . . . . . . . . . . . . . . . . . . . . . 79
I port output timing . . . . . . . . . . . . . . . . . . . . . 79
SAF7118
© NXP B.V. 2008. All rights reserved.
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