3341-54 Peregrine Semiconductor, 3341-54 Datasheet - Page 12

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3341-54

Manufacturer Part Number
3341-54
Description
IC PLL INTEGER-N 2.7GHZ 20QFN
Manufacturer
Peregrine Semiconductor
Series
UltraCMOS™r
Type
PLL Clock Driverr
Datasheet

Specifications of 3341-54

Input
Clock
Output
Clock
Frequency - Max
2.7GHz
Voltage - Supply
2.85 V ~ 3.15 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-VFQFN Exposed Pad
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Figure 8. Details of EE register contents loaded from EEPROM and then shifted out Serially through
Dout pin - The procedure is performed twice.
In Figure 8, the first step is to program
Enhancement Register to set Bit 1 high (“1”) to
access EE Register Output Bit Function.
Subsequent action, which includes pulses, allows
the existing EE Register contents to be shifted out
the Dout pin and the EEPROM contents are
loaded to the EE Register. Since the initial data
existing in the EE Register could be anything, the
data must be flushed out before clocking the
©2005-8 Peregrine Semiconductor Corp. All rights reserved.
Page 12 of 17
Note: ENH/ (Pin 20) is at low (0) for this process.
EELoad
(example)
E_WR
S_WR
EESel
Data
Clock
Dout
Enhancement
Programming
3V
3V
0V
0V
0V
3V
3V
0V
0V
3V
0V
3V
0V
Register
EE Register
EEPROM
load from
0 1 0 1 0 0 1 1 1 1 1 0 0 0 1 1 1 0 0 1
through Dout
EE Register
shifted out
Rough time scale
contents of the EEPROM register out. After the
same procedures are duplicated, the Dout output
is the EEPROM content. Note that only 19 Clock
pulses are enough for the 20-bit EE Register
because the first bit data is already present at
Dout pin. Also ENH/ (Pin 20) is set to low (“0”) to
access the Enhancement
Document No. 70-0053-05 │ UltraCMOS™ RFIC Solutions
20 us
mode.
Product Specification
PE3341

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