83336-22 Peregrine Semiconductor, 83336-22 Datasheet - Page 6

• Manufacturer Part Number: 83336-22
• Description: IC PLL INTEGER-N 3GHZ 44CQFJ
• Manufacturer: Peregrine Semiconductor
• Series: UltraCMOS™r
• Type: PLL Clock Driverr

Specifications of 83336-22

• Input: Clock
• Output: Clock
• Frequency - Max: 3GHz
• Voltage - Supply: 2.85 V ~ 3.15 V
• Operating Temperature: -55°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 44-CLCC Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 6. AC Characteristics:
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 6 of 13
Control Interface and Latches (see Figures 4, 5, 6)
Main Divider (Including Prescaler)
Main Divider (Prescaler Bypassed)
Reference Divider
Phase Detector
SSB Phase Noise : Output Referred (F
Symbol
PN
PN
t
t
t
t
t
t
t
P
P
DHLD
t
CWR
WRC
MDO
f
ClkH
t
t
F
F
P
V
ClkL
DSU
Clk
PW
CE
EC
f
f
Fin
Fin
r
c
in
in
fr
fr
OR
OR
Parameter is guaranteed through characterization only and is not tested.
Running at low frequencies (< 10 MHz sinewave), the device will still be functional but may cause phase noise degradation. Inserting a low-
noise amplifier to square up the edges is recommended at lower input frequencies.
CMOS logic levels may be used if DC coupled. For optimum phase noise performance, the reference input falling edge rate should be faster
than 80mV/ns.
All devices are screened to phase noise limits listed in Table 7. The magnitude of the tester uncertainty precludes testing phase noise as
part of qualification testing. These parameters are also exempt from PDA requirements.
Parameter is tested using 100pF load capacitance and is guaranteed through characterization only. Typical test delay is 12nS.
Serial data clock frequency
Serial clock HIGH time
Serial clock LOW time
Sdata set-up time after Sclk rising edge, D[7:0] set-up
time to M1_WR, M2_WR, A_WR, E_WR rising edge
Sdata hold time after Sclk rising edge, D[7:0] hold time to
M1_WR, M2_WR, A_WR, E_WR rising edge
S_WR, M1_WR, M2_WR, A_WR, E_WR pulse width
Sclk rising edge to S_WR rising edge. S_WR, M1_WR,
M2_WR, A_WR falling edge to Hop_WR rising edge
Sclk falling edge to E_WR transition
S_WR falling edge to Sclk rising edge. Hop_WR falling
edge to S_WR, M1_WR, M2_WR, A_WR rising edge
E_WR transition to Sclk rising edge
MSEL data out delay after Fin rising edge
Operating frequency
Input level range
Operating frequency
Input level range
Operating frequency
Reference input power
Input sensitivity
Comparison frequency
Output Referred Phase Noise
Output Referred Phase Noise
Parameter
in
V
= 1918MHz, f
DD
= 3.0 V, -55° C ≤ T
r
= 10 MHz, f
c
A
= 1MHz, LBW = 70 kHz
≤ 125° C, unless otherwise specified
C
External AC coupling
External AC coupling
85 C < T
External AC coupling
External AC coupling
85 C < T
(Note 1)
Single ended input
External AC coupling
(Note 3)
(Note 1)
100 Hz Offset:
V
1000 Hz Offset:
V
DD
DD
L
= 12 pf
= 3.0V, T = 25ºC
= 3.0V, T = 25ºC
Conditions
A
A
≤ 125 C
≤ 125 C
Document No. 70-0137-02 │ UltraCMOS™ RFIC Solutions
)
(Note 2)
Min
500
0.5
30
30
10
10
30
30
30
30
30
50
-5
-5
-2
0
0
Typ
-78
-94
8
(Note 4)
(Note 4)
(Note 5)
Max
3000
300
100
Product Specification
10
10
20
5
5
5
5
PE83336
dBc/Hz
dBc/Hz
Units
MHz
MHz
dBm
dBm
MHz
dBm
dBm
MHz
dBm
MHz
V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
P-P