5962-8764801XA QP SEMICONDUCTOR, 5962-8764801XA Datasheet - Page 5

• Manufacturer Part Number: 5962-8764801XA
• Manufacturer: QP SEMICONDUCTOR

Specifications of 5962-8764801XA

• Lead Free Status / Rohs Status: Supplier Unconfirmed

DSCC FORM 2234
APR 97
option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made
available onshore at the option of the reviewer.
microcircuit group number 42 (see MIL-PRF-38535, appendix A).
manufacturer prior to delivery.
specified in 4.5 herein.
procedures and characteristics specified in 4.6 herein.
programmed to the specified pattern or erased. As a minimum, verification shall consist of performing a functional test
(subgroup 7) to verify that all bits are in the proper state. Any bit that does not verify to be in the proper state shall constitute a
device failure, and shall be removed from the lot.
be done for initial characterization and after any design or process changes which may affect data retention. The methods and
procedures may be vendor specific but shall guarantee data retention over the full military temperature range. The vendor's
procedure shall be kept under document control and shall be made available upon request of the aquiring or preparing activity,
along with test data.
MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan
shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in
accordance with MIL-PRF-38535, appendix A.
on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in
accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection.
3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain the
3.11 Processing EPROMs. All testing requirements and quality assurance provisions herein shall be satisfied by the
3.11.1 Erasure of EPROMs. When specified, devices shall be erased in accordance with the procedure and characteristics
3.11.2 Programmability of EPROMs. When specified, devices shall be programmed to the specified pattern using the
3.11.3 Verification of erasure and/or programmability of EPROMs. When specified devices shall be verified as either
3.12 Data retention. A data retention stress test shall be completed as part of the vendor's reliability monitors. This test shall
4.2.1 Additional criteria for device class M.
4.2.2 Additional criteria for device classes Q and V.
3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in
4. VERIFICATION
4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with
4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted
a. Burn-in test, method 1015 of MIL-STD-883.
b. Interim and final electrical test parameters shall be as specified in table IIA herein.
a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the device
b. Interim and final electrical test parameters shall be as specified in table IIA herein.
c. Additional screening for device class V beyond the requirements of device class Q shall be as specified in MIL-PRF-
(1) Test condition C or D. The test circuit shall be maintained by the manufacturer under document revision level control
(2) T A = +125°C, minimum.
manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under document
revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with MIL-PRF-38535
and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs,
outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-
883.
38535, appendix B.
DEFENSE SUPPLY CENTER COLUMBUS
and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015
of MIL-STD-883.
MICROCIRCUIT DRAWING
COLUMBUS, OHIO 43218-3990
STANDARD
SIZE
A
REVISION LEVEL
E
SHEET
5962-87648
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