LH28F800BVE-TV85 Sharp Electronics, LH28F800BVE-TV85 Datasheet - Page 9

• Manufacturer Part Number: LH28F800BVE-TV85
• Manufacturer: Sharp Electronics

Specifications of LH28F800BVE-TV85

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 85ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 20/19Bit
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8/16Bit
• Number Of Words: 1M/512K
• Supply Current: 65mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

2 PRINCIPLES OF OPERATION
The LH28F800BVE-TV85 Smart5 Flash memory includes
an on-chip WSM to manage block erase and word/byte
write functions. It allows for: 100% TTL-level control
inputs, fixed power supplies during block erasure and
word/byte write, and minimal processor overhead with
RAM-like interface timings.
After initial device power-up or return from deep power-
down mode (see Bus Operations), the device defaults to
read array mode. Manipulation of external memory control
pins allow array read, standby and output disable
operations.
Status register and identifier codes can be accessed
through the CUI independent of the V
voltage on V
word/byte writing. All functions associated with altering
memory contents−block erase, word/byte write, status and
identifier codes−are accessed via the CUI and verified
through the status register.
Commands are written using standard microprocessor
write timings. The CUI contents serve as input to the
WSM, which controls the block erase and word/byte write.
The internal algorithms are regulated by the WSM,
including pulse repetition, internal verification and
margining of data. Addresses and data are internally latch
during write cycles. Writing the appropriate command
outputs array data, accesses the identifier codes or outputs
status register data.
Interface software that initiates and polls progress of block
erase and word/byte write can be stored in any block. This
code is copied to and executed from system RAM during
flash memory updates. After successful completion, reads
are again possible via the Read Array command. Block
erase suspend allows system software to suspend a block
erase to read/write data from/to blocks other than that
which is suspend. Word/byte write suspend allows system
software to suspend a word/byte write to read data from
any other flash memory array location.
PP
enables successful block erasure and
PP
voltage. High
[
A
7DFFF
7CFFF
7FFFF
7EFFF
7BFFF
7AFFF
6FFFF
5FFFF
4FFFF
3FFFF
2FFFF
1FFFF
0FFFF
18
7E000
7D000
7C000
7B000
7A000
79FFF
78FFF
77FFF
67FFF
57FFF
47FFF
37FFF
27FFF
17FFF
07FFF
7F000
79000
78000
70000
68000
60000
58000
50000
48000
40000
38000
30000
28000
20000
18000
10000
08000
00000
-A
0
]
Figure 3. Memory Map
4K-word Parameter Block
4K-word Parameter Block
4K-word Parameter Block
4K-word Parameter Block
4K-word Parameter Block
4K-word Parameter Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
32K-word Main Block
4K-word Boot Block
4K-word Boot Block
Top Boot
10
13
11
12
14
0
1
0
1
2
3
4
5
0
1
2
3
4
5
6
7
8
9
Rev. 1.2