LH28F800BJE-PBTL90 Sharp Electronics, LH28F800BJE-PBTL90 Datasheet - Page 9

• Manufacturer Part Number: LH28F800BJE-PBTL90
• Manufacturer: Sharp Electronics

Specifications of LH28F800BJE-PBTL90

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 90ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 20/19Bit
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 1M/512K
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

2 PRINCIPLES OF OPERATION
The product includes an on-chip WSM to manage block
erase, full chip erase, word/byte write and lock-bit
configuration functions. It allows for: fixed power supplies
during block erase, full chip erase, word/byte write and
lock-bit configuration, and minimal processor overhead
with RAM-like interface timings.
After initial device power-up or return from reset mode
(see section 3 Bus Operations), the device defaults to read
array mode. Manipulation of external memory control pins
allow array read, standby and output disable operations.
Status register and identifier codes can be accessed
through the CUI independent of the V
voltage on V
erase, word/byte write and lock-bit configurations. All
functions associated with altering memory contents−block
erase,
configuration, status and identifier codes−are accessed via
the CUI and verified through the status register.
Commands are written using standard microprocessor
write timings. The CUI contents serve as input to the
WSM, which controls the block erase, full chip erase,
word/byte write and lock-bit configuration. The internal
algorithms are regulated by the WSM, including pulse
repetition, internal verification and margining of data.
Addresses and data are internally latched during write
cycles. Writing the appropriate command outputs array
data, accesses the identifier codes or outputs status register
data.
Interface software that initiates and polls progress of block
erase, full chip erase, word/byte write and lock-bit
configuration can be stored in any block. This code is
copied to and executed from system RAM during flash
memory updates. After successful completion, reads are
again possible via the Read Array command. Block erase
suspend allows system software to suspend a block erase
to read/write data from/to blocks other than that which is
suspend. Word/byte write suspend allows system software
to suspend a word/byte write to read data from any other
flash memory array location.
full
CCW
chip
enables successful block erase, full chip
erase,
word/byte
CCW
write,
voltage. High
lock-bit
[A
7FFFF
6FFFF
5FFFF
4FFFF
3FFFF
2FFFF
1FFFF
0FFFF
77FFF
67FFF
57FFF
47FFF
37FFF
27FFF
17FFF
07FFF
06FFF
05FFF
04FFF
03FFF
02FFF
01FFF
00FFF
18
78000
70000
68000
60000
58000
50000
48000
40000
38000
30000
28000
20000
18000
10000
08000
07000
06000
05000
04000
03000
02000
01000
00000
-A
0
]
Figure 3. Memory Map
4KW/8KB Parameter Block
4KW/8KB Parameter Block
4KW/8KB Parameter Block
4KW/8KB Parameter Block
4KW/8KB Parameter Block
4KW/8KB Parameter Block
32KW/64KB Main Block
32KW/64KB Main Block
32KW/64KB Main Block
32KW/64KB Main Block
32KW/64KB Main Block
32KW/64KB Main Block
32KW/64KB Main Block
32KW/64KB Main Block
32KW/64KB Main Block
32KW/64KB Main Block
32KW/64KB Main Block
32KW/64KB Main Block
32KW/64KB Main Block
32KW/64KB Main Block
32KW/64KB Main Block
4KW/8KB Boot Block
4KW/8KB Boot Block
Bottom Boot
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
5
4
3
2
1
0
1
0
[A
0DFFFF
0D0000
0CFFFF
0C0000
0BFFFF
0B0000
0AFFFF
0A0000
07FFFF
070000
06FFFF
060000
05FFFF
050000
04FFFF
040000
03FFFF
030000
02FFFF
020000
0FFFFF
0F0000
0EFFFF
0E0000
09FFFF
090000
08FFFF
080000
01FFFF
010000
00FFFF
00E000
00DFFF
00C000
00BFFF
00A000
009FFF
008000
007FFF
006000
005FFF
004000
003FFF
002000
001FFF
000000
18
Rev. 1.27
-A
-1
]