LH28F800BJHE-PTTLT6 Sharp Electronics, LH28F800BJHE-PTTLT6 Datasheet - Page 30
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LH28F800BJHE-PTTLT6
Manufacturer Part Number
LH28F800BJHE-PTTLT6
Description
Manufacturer
Sharp Electronics
Datasheet
1.LH28F800BJHE-PTTLT6.pdf
(58 pages)
Specifications of LH28F800BJHE-PTTLT6
Cell Type
NOR
Density
8Mb
Access Time (max)
90ns
Interface Type
Parallel
Boot Type
Top
Address Bus
20/19Bit
Operating Supply Voltage (typ)
3/3.3V
Operating Temp Range
-40C to 85C
Package Type
TSOP
Sync/async
Asynchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8/16Bit
Number Of Words
1M/512K
Supply Current
30mA
Mounting
Surface Mount
Pin Count
48
Lead Free Status / Rohs Status
Compliant
5 DESIGN CONSIDERATIONS
5.1 Three-Line Output Control
The device will often be used in large memory arrays.
SHARP provides three control inputs to accommodate
multiple memory connections. Three-line control provides
for:
To use these control inputs efficiently, an address decoder
should enable CE# while OE# should be connected to all
memory devices and the system’s READ# control line.
This assures that only selected memory devices have
active outputs while deselected memory devices are in
standby mode. RP# should be connected to the system
POWERGOOD signal to prevent unintended writes during
system power transitions. POWERGOOD should also
toggle during system reset.
5.2 RY/BY# and WSM Polling
RY/BY# is an open drain output that should be connected
to V
of detecting block erase, full chip erase, word/byte write
and lock-bit configuration completion. It transitions low
after block erase, full chip erase, word/byte write or lock-
bit configuration commands and returns to V
RY/BY# is pull up) when the WSM has finished executing
the internal algorithm.
RY/BY# can be connected to an interrupt input of the
system CPU or controller. It is active at all times. RY/BY#
is also High Z when the device is in block erase suspend
(with word/byte write inactive), word/byte write suspend
or reset modes.
a. Lowest possible memory power dissipation.
b. Complete assurance that data bus contention will not
CC
occur.
by a pull up resistor to provides a hardware method
OH
(while
5.3 Power Supply Decoupling
Flash memory power switching characteristics require
careful device decoupling. System designers are interested
in three supply current issues; standby current levels,
active current levels and transient peaks produced by
falling and rising edges of CE# and OE#. Transient current
magnitudes depend on the device outputs’ capacitive and
inductive loading. Two-line control and proper decoupling
capacitor selection will suppress transient voltage peaks.
Each device should have a 0.1µF ceramic capacitor
connected between its V
V
capacitors should be placed as close as possible to package
leads. Additionally, for every eight devices, a 4.7µF
electrolytic capacitor should be placed at the array’s power
supply connection between V
capacitor will overcome voltage slumps caused by PC
board trace inductance.
5.4 V
Updating flash memories that reside in the target system
requires that the printed circuit board designer pay
attention to the V
supplies the memory cell current for word/byte writing
and block erasing. Use similar trace widths and layout
considerations given to the V
V
voltage spikes and overshoots.
5.5 V
Block erase, full chip erase, word/byte write and lock-bit
configuration are not guaranteed if V
valid V
3.6V range, or RP#≠V
register bit SR.3 is set to "1" along with SR.4 or SR.5,
depending on the attempted operation. If RP# transitions
to V
or lock-bit configuration, RY/BY# will remain low until
the reset operation is complete. Then, the operation will
abort and the device will enter reset mode. The aborted
operation may leave data partially altered. Therefore, the
command sequence must be repeated after normal
operation is restored. Device power-off or RP# transitions
to V
The CUI latches commands issued by system software and
is not altered by V
actions. Its state is read array mode upon power-up, after
exit from reset mode or after V
CCW
CCW
IL
IL
clear the status register.
during block erase, full chip erase, word/byte write
supply traces and decoupling will decrease V
and GND. These high-frequency, low inductance
CCWH1/2
CCW
CC
, V
Trace on Printed Circuit Boards
CCW
range, V
CCW
, RP# Transitions
CCW
IH
Power supply trace. The V
. If V
CC
CC
or CE# transitions or WSM
falls outside of a valid 2.7V-
CCW
and GND and between its
CC
CC
CC
transitions below V
error is detected, status
power bus. Adequate
and GND. The bulk
CCW
falls outside of a
Rev. 1.27
CCW
LKO
CCW
pin
.