LH28F008BJT-BTLZ1 Sharp Electronics, LH28F008BJT-BTLZ1 Datasheet - Page 14

• Manufacturer Part Number: LH28F008BJT-BTLZ1
• Manufacturer: Sharp Electronics

Specifications of LH28F008BJT-BTLZ1

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 100ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 20b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

NOTES:
1. BUS operations are defined in Table 2.
2. X=Any valid address within the device.
3. ID=Data read from identifier codes.
4. Following the Read Identifier Codes command, read operations access manufacturer, device, block lock configuration and
5. If WP# is V
6. Either 40H or 10H are recognized by the WSM as the byte write setup.
7. The clear block lock-bits operation simultaneously clears all block lock-bits.
8. If the permanent lock-bit is set, Set Block Lock-Bit and Clear Block Lock-Bits commands can not be done.
9. Once the permanent lock-bit is set, permanent lock-bit reset is unable.
10. Commands other than those shown above are reserved by SHARP for future device implementations and should not be
Read Array/Reset
Read Identifier Codes
Read Status Register
Clear Status Register
Block Erase
Full Chip Erase
Byte Write
Block Erase and Byte Write
Suspend
Block Erase and Byte Write
Resume
Set Block Lock-Bit
Clear Block Lock-Bits
Set Permanent Lock-Bit
sharp
IA=Identifier Code Address: see Figure 4.
BA=Address within the block being erased or locked.
WA=Address of memory location to be written.
SRD=Data read from status register. See Table 6 for a description of the status register bits.
WD=Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first).
permanent lock configuration codes. See Section 4.2 for read identifier code data.
bits. The parameter and main blocks are locked by block lock-bits without WP# state.
used.
Command
IL
, boot blocks are locked without block lock-bits state. If WP# is V
Bus Cycles
Req’d.
≥2
1
2
1
2
2
2
1
1
2
2
2
Table 3. Command Definitions
Notes
5,6
7,8
4
5
5
5
8
9
LHF08JZ1
Oper
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
(1)
First Bus Cycle
Addr
X
X
X
X
X
X
X
X
X
X
X
X
(2)
(10)
Data
40H or
D0H
IH
FFH
B0H
90H
70H
50H
20H
30H
10H
60H
60H
60H
, boot blocks are locked by block lock-
(3)
Oper
Write
Write
Write
Write
Write
Write
Read
Read
(1)
Second Bus Cycle
Addr
WA
BA
BA
IA
X
X
X
X
(2)
Rev. 1.27
Data
SRD
D0H
D0H
D0H
F1H
WD
01H
ID
(3)
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