LH28F160S5NS-L10 Sharp Electronics, LH28F160S5NS-L10 Datasheet - Page 46
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LH28F160S5NS-L10
Manufacturer Part Number
LH28F160S5NS-L10
Description
Manufacturer
Sharp Electronics
Datasheet
1.LH28F160S5NS-L10.pdf
(63 pages)
Specifications of LH28F160S5NS-L10
Cell Type
NOR
Density
16Mb
Access Time (max)
100ns
Interface Type
Parallel
Boot Type
Not Required
Address Bus
21/20Bit
Operating Supply Voltage (typ)
5V
Operating Temp Range
0C to 70C
Package Type
SSOP
Program/erase Volt (typ)
4.5 to 5.5V
Sync/async
Asynchronous
Operating Temperature Classification
Commercial
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Word Size
8/16Bit
Number Of Words
2M/1M
Supply Current
65mA
Mounting
Surface Mount
Pin Count
56
Lead Free Status / Rohs Status
Not Compliant
sharp
6.2.7 RESET OPERATIONS
NOTES:
1. If RP# is asserted while a block erase, full chip erase, (multi) word/byte write or block lock-bit configuration
2. A reset time, t
3. When the device power-up, holding RP# low minimum 100ns is required after V
Symbol
t
t
t
PLPH
PLRH
5VPH
operation is not executing, the reset will complete within 100ns.
and also has been in stable there.
RP# Pulse Low Time
(If RP# is tied to V
RP# Low to Reset during Block Erase, Full Chip Erase,
(Multi) Word/Byte Write or Block Lock-Bit Configuration
V
CC
at 4.5V to RP# High
PHQV
STS(R)
STS(R)
RP#(P)
RP#(P)
RP#(P)
V
CC
, is required from the latter of STS going High Z or RP# going high until outputs are valid.
High Z
High Z
V
V
V
V
V
V
5V
V
V
V
OL
OL
IH
IL
IH
IL
IH
IL
IL
CC
, this specification is not applicable)
Figure 21. AC Waveform for Reset Operation
Parameter
(B)Reset During Block Erase, Full Chip Erase, (Multi) Word/Byte Write
t
t
PLPH
PLPH
or Block Lock-Bit Configuretion
Reset AC Specifications
(A)Reset During Read Array Mode
LHF16KA9
(C)V
t
PLRH
t
5VPH
CC
Power Up Timing
Notes
1,2
3
CC
Min.
100
100
has been in predefined range
V
CC
=5V
Max.
13.1
Rev. 2.0
Unit
ns
µs
ns
43