LH28F640BFN-PTTLZ1 Sharp Electronics, LH28F640BFN-PTTLZ1 Datasheet - Page 11

• Manufacturer Part Number: LH28F640BFN-PTTLZ1
• Manufacturer: Sharp Electronics

Specifications of LH28F640BFN-PTTLZ1

• Cell Type: NOR
• Density: 64Mb
• Access Time (max): 80ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 22b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: SOP
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 4M
• Supply Current: 25mA
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Not Compliant

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NOTES:
1. Bus operations are defined in Table 3.
2. The address which is written at the first bus cycle should be the same as the address which is written at the second bus
3. ID=Data read from identifier codes. (See Table 2).
4. Following the Read Identifier Codes/OTP command, read operations access manufacturer code, device code, block lock
5. Block erase, full chip erase or (page buffer) program cannot be executed when the selected block is locked. Unlocked
6. Either 40H or 10H are recognized by the CUI (Command User Interface) as the program setup.
7. Following the third bus cycle, inputs the program sequential address and write data of "N" times. Finally, input the any
8. Full chip erase and OTP program operations can not be suspended. The OTP Program command can not be accepted
Read Array
Read Identifier Codes/OTP
Read Query
Read Status Register
Clear Status Register
Block Erase
Full Chip Erase
Program
Page Buffer Program
Block Erase and (Page Buffer)
Block Erase and (Page Buffer)
Set Block Lock Bit
Clear Block Lock Bit
Set Block Lock-down Bit
OTP Program
Program Suspend
Program Resume
cycle.
X=Any valid address within the device.
IA=Identifier codes address (See Table 2).
QA=Query codes address. Refer to Appendix of LH28F640BF series for details.
BA=Address within the block being erased, set/cleared block lock bit or set block lock-down bit.
WA=Address of memory location for the Program command or the first address for the Page Buffer Program command.
OA=Address of OTP block to be read or programmed (See Figure 3).
QD=Data read from query database. Refer to Appendix of LH28F640BF series for details.
SRD=Data read from status register. See Table 7 and Table 8 for a description of the status register bits.
WD=Data to be programmed at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes
OD=Data to be programmed at location OA. Data is latched on the rising edge of WE# or CE# (whichever goes
N-1=N is the number of the words to be loaded into a page buffer.
configuration code, and the data within OTP block (See Table 2).
The Read Query command is available for reading CFI (Common Flash Interface) information.
block can be erased or programmed when RST# is V
valid address within the target block to be programmed and the confirm command (D0H). Refer to Appendix of
LH28F640BF series for details.
high first).
high first).
Command
Cycles
Req’d
Bus
≥ 2
≥ 2
≥ 4
1
2
1
2
2
2
1
1
2
2
2
2
Table 4. Command Definitions
2,3,5,6
2,3,5,7
Notes
2,3,11
2,3,4
2,3,4
2,3,5
2,5,8
2,3,8
2,8
2,8
2,9
2
2
2
2
LHF64FD1
IH
Oper
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
.
(1)
First Bus Cycle
BA or WA
BA or WA
BA or WA
Addr
WA
WA
BA
BA
BA
BA
OA
X
X
X
X
X
(2)
(10)
Data
40H or
B0H
D0H
C0H
FFH
20H
E8H
60H
60H
60H
90H
98H
70H
50H
30H
10H
(3)
Oper
Write
Write
Write
Write
Write
Write
Write
Write
Read
Read
Read
(1)
Second Bus Cycle
BA or WA
IA or OA
Addr
WA
WA
QA
BA
BA
BA
BA
OA
X
(2)
Rev. 2.41
ID or OD
Data
SRD
D0H
D0H
D0H
01H
2FH
WD
N-1
QD
OD
(3)
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