A1460A-3PQ208C MICROSEMI, A1460A-3PQ208C Datasheet - Page 12

• Manufacturer Part Number: A1460A-3PQ208C
• Manufacturer: MICROSEMI

Specifications of A1460A-3PQ208C

• Number Of Usable Gates: 6000
• Number Of Logic Blocks/elements: 848
• # Registers: 768
• # I/os (max): 167
• Frequency (max): 200MHz
• Process Technology: 0.8um (CMOS)
• Operating Supply Voltage (typ): 5V
• Logic Cells: 848
• Device System Gates: 15000
• Propagation Delay Time: 2ns
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Antifuse Connections
An antifuse is a “normally open” structure as opposed to the
normally closed fuse structure used in PROMs or PALs. The
use of antifuses to implement a programmable logic device
results in highly testable structures as well as an efficient
programming architecture. The structure is highly testable
because there are no preexisting connections; temporary
connections can be made using pass transistors. These
temporary connections can isolate individual antifuses to be
programmed as well as isolate individual circuit structures to
be tested. This can be done both before and after
programming. For example, all metal tracks can be tested for
continuity and shorts between adjacent tracks, and the
functionality of all logic modules can be verified.
Four types of antifuse connections are used in the routing
structure of the ACT 3 array. (The physical structure of the
antifuse is identical in each case; only the usage differs.)
Table 1 shows four types of antifuses.
Table 1 • Antifuse Types
Examples of all four types of connections are shown in
Figures 7 and 8.
Module Interface
Connections to Logic and I/O modules are made through
vertical segments that connect to the module inputs and
outputs. These vertical segments lie on vertical tracks that
span the entire height of the array.
Module Input Connections
The tracks dedicated to module inputs are segmented by pass
transistors in each module row. During normal user
operation, the pass transistors are inactive, which isolates the
inputs of a module from the inputs of the module directly
above or below it. During certain test modes, the pass
transistors are active to verify the continuity of the metal
tracks. Vertical input segments span only the channel above
1-186
XF
HF
VF
FF
Horizontal-to-Vertical Connection
Horizontal-to-Horizontal Connection
Vertical-to-Vertical Connection
“Fast” Vertical Connection
or the channel below. The logic modules are arranged such
that half of the inputs are connected to the channel above
and half of the inputs to segments in the channel below as
shown in Figure 9.
Module Output Connections
Module outputs have dedicated output segments. Output
segments extend vertically two channels above and two
channels below, except at the top or bottom of the array.
Output segments twist, as shown in Figure 10, so that only
four vertical tracks are required.
LVT Connections
Outputs may also connect to nondedicated segments called
Long Vertical Tracks (LVTs). Each module pair in the array
shares four LVTs that span the length of the column. Any
module in the column pair can connect to one of the LVTs in
the column using an FF connection. The FF connection uses
antifuses connected directly to the driver stage of the module
output, bypassing the isolation transistor. FF antifuses are
programmed at a higher current level than HF, VF, or XF
antifuses to produce a lower resistance value.
Antifuse Connections
In general every intersection of a vertical segment and a
horizontal segment contains an unprogrammed antifuse
(XF-type). One exception is in the case of the clock networks.
Clock Connections
To minimize loading on the clock networks, a subset of inputs
has antifuses on the clock tracks. Only a few of the C-module
and S-module inputs can be connected to the clock networks.
To further reduce loading on the clock network, only a subset
of the horizontal routing tracks can connect to the clock
inputs of the S-module.
Programming and Test Circuits
The array of logic and I/O modules is surrounded by test and
programming circuits controlled by the temporary special I/O
pins MODE, SDI, and DCLK. The function of these pins is
similar to all ACT family devices. The ACT 3 family also
includes support for two Actionprobe
complete observability of any logic or I/O module in the array
using the temporary special I/O pins, PRA and PRB.
®
circuits allowing