A1460A-3PQ208C MICROSEMI, A1460A-3PQ208C Datasheet - Page 29

• Manufacturer Part Number: A1460A-3PQ208C
• Manufacturer: MICROSEMI

Specifications of A1460A-3PQ208C

• Number Of Usable Gates: 6000
• Number Of Logic Blocks/elements: 848
• # Registers: 768
• # I/os (max): 167
• Frequency (max): 200MHz
• Process Technology: 0.8um (CMOS)
• Operating Supply Voltage (typ): 5V
• Logic Cells: 848
• Device System Gates: 15000
• Propagation Delay Time: 2ns
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

A 1425 A, A 14V25 A T i m i ng Ch ar a c t e r is tic s
(Worst-Case Commercial Conditions, V
Notes:
1.
2.
3.
Logic Module Propagation Delays
Parameter
t
t
t
Predicted Routing Delays
t
t
t
t
t
Logic Module Sequential Timing
t
t
t
t
t
t
t
f
PD
CO
CLR
RD1
RD2
RD3
RD4
RD8
SUD
HD
SUD
HD
WASYN
WCLKA
A
MAX
V
For dual-module macros, use t
Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based
on actual routing delay measurements performed on the device prior to shipment.
CC
= 3.0 V for 3.3V specifications.
Description
Internal Array Module
Sequential Clock to Q
Asynchronous Clear to Q
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
Flip-Flop Data Input Setup
Flip-Flop Data Input Hold
Latch Data Input Setup
Latch Data Input Hold
Asynchronous Pulse Width
Flip-Flop Clock Pulse Width
Flip-Flop Clock Input Period
Flip-Flop Clock Frequency
3
PD
+ t
RD1
2
+ t
PDn
, t
Min.
CO
‘–3’ Speed
0.5
0.0
0.5
0.0
1.9
1.9
4.0
+ t
CC
RD1
Max.
250
= 4.75 V, T
2.0
2.0
2.0
0.9
1.2
1.4
1.7
2.8
+ t
PDn
or t
Min.
‘–2’ Speed
0.6
0.0
0.6
0.0
2.4
2.4
5.0
PD1
+ t
Max.
200
2.3
2.3
2.3
1.0
1.4
1.6
1.9
3.2
J
RD1
A cceler ator Se rie s FP GAs – A CT
= 70 C)
+ t
SUD
Min.
‘–1’ Speed
0.7
0.0
0.7
0.0
3.2
3.2
6.8
, whichever is appropriate.
1
Max.
150
2.6
2.6
2.6
1.1
1.6
1.8
2.2
3.6
‘Std’ Speed 3.3V Speed
Min.
0.8
0.0
0.8
0.0
3.8
3.8
8.0
Max.
125
3.0
3.0
3.0
1.3
1.8
2.1
2.5
4.2
Min.
10.0
0.8
0.0
0.8
0.0
4.8
4.8
Max. Units
™
100
3.9
3.9
3.9
1.7
2.4
2.8
3.3
5.5
3 Fami ly
1
MHz
1-203
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns