CY7B993V-5AC Cypress Semiconductor Corp, CY7B993V-5AC Datasheet - Page 6

• Manufacturer Part Number: CY7B993V-5AC
• Manufacturer: Cypress Semiconductor Corp
• Type: Zero Delay PLL Clock Bufferr

Specifications of CY7B993V-5AC

• Number Of Elements: 1
• Supply Current: 250mA
• Pll Input Freq (min): 12MHz
• Pll Input Freq (max): 100MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TQFP
• Output Frequency Range: 12 to 100MHz
• Operating Supply Voltage (min): 2.97V
• Operating Supply Voltage (max): 3.63V
• Operating Temperature Classification: Commercial
• Pin Count: 100
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-07127 Rev. *F
Output Disable Description
The feedback Divide and Phase Select Matrix Bank has two
outputs, and each of the four Divide and Phase Select Matrix
Banks have four outputs. The outputs of each bank can be
independently put into a HOLD-OFF or high-impedance state.
The combination of the OUTPUT_MODE and DIS[1:4]/FBDIS
inputs determines the clock outputs’ state for each bank. When
the DIS[1:4]/FBDIS is LOW, the outputs of the corresponding
bank will be enabled. When the DIS[1:4]/FBDIS is HIGH, the
outputs for that bank will be disabled to a high-impedance
(HI-Z) or HOLD-OFF state depending on the OUTPUT_MODE
input. Table 5 defines the disabled output functions.
The HOLD-OFF state is intended to be a power saving feature.
An output bank is disabled to the HOLD-OFF state in a
maximum of six output clock cycles from the time when the
disable input (DIS[1:4]/FBDIS) is HIGH. When disabled to the
Note:
(N/A)
(N/A)
(N/A)
4. FB connected to an output selected for “Zero” skew (i.e., FBF0 = MID or XF[1:0] = MID).
1F[1:0]
2F[1:0]
(N/A)
(N/A)
(N/A)
MM
LM
LH
ML
MH
LL
HL
HM
HH
(N/A)
(N/A)
(N/A)
(N/A)
(N/A)
(N/A)
(N/A)
(N/A)
3F[1:0]
4F[1:0]
MM
HL
LL
LM
HM
LH
HH
REFInput
FBInput
+1t
+2t
+3t
+6t
+7t
+8t
–2t
+4t
–8t
–7t
–6t
–4t
–3t
–1t
0t
Figure 1. Typical Outputs with FB Connected to a Zero-Skew Output
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
HOLD-OFF state, non-inverting outputs are driven to a logic
LOW state on its falling edge. Inverting outputs are driven to a
logic HIGH state on its rising edge. This ensures the output
clocks are stopped without glitch. When a bank of outputs is
disabled to HI-Z state, the respective bank of outputs will go
HI-Z immediately.
Table 5. DIS[1:4]/FBDIS Pin Functionality
OUTPUT_MODE
HIGH/LOW
HIGH
LOW
MID
DIS[1:4]/FBDIS
HIGH
HIGH
LOW
X
[4]
RoboClock
CY7B993V
CY7B994V
FACTORY TEST
Output Mode
HOLD-OFF
ENABLED
Page 6 of 15
HI-Z
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