CY7C028V-15AC Cypress Semiconductor Corp, CY7C028V-15AC Datasheet - Page 10

• Manufacturer Part Number: CY7C028V-15AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C028V-15AC

• Density: 1Mb
• Access Time (max): 15ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 16b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 185mA
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 16b
• Number Of Words: 64K
• Lead Free Status / Rohs Status: Not Compliant

Switching Waveforms
Document #: 38-06078 Rev. *B
Notes
CE
20. R/W must be HIGH during all address transitions.
21. A write occurs during the overlap (t
22. t
23. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
24. To access RAM, CE = V
25. To access upper byte, CE = V
26. Transition is measured ±500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled and not 100% tested.
27. During this period, the I/O pins are in the output state, and input signals must not be applied.
28. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state.
DATA OUT
ADDRESS
ADDRESS
CE
DATA IN
DATA IN
[24,25]
HA
the bus for the required t
To access lower byte, CE = V
[24,25]
is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
R/W
R/W
OE
SD
IL
, SEM = V
. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t
IL
, LB = V
IL
, UB = V
t
t
SA
SA
Figure 7. Write Cycle No. 1: R/W Controlled Timing
NOTE 27
Figure 8. Write Cycle No. 2: CE Controlled Timing
(continued)
IH
SCE
.
IL
, SEM = V
IL
or t
, SEM = V
PWE
) of a LOW CE or SEM and a LOW UB or LB.
IH
.
IH
t
HZWE
.
[26]
t
t
AW
AW
t
t
WC
WC
t
t
SCE
PWE
[23]
PWE
t
t
SD
SD
or (t
HZWE
+ t
CY7C027V/027VN/027AV/028V
SD
t
t
) to allow the I/O drivers to turn off and data to be placed on
HA
HA
[20, 21, 22, 28]
[20, 21, 22, 23]
t
t
HD
HD
t
LZWE
CY7C037V/037AV/038V
t
HZOE
NOTE 27
[26]
Page 10 of 18
PWE
.
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