CY7C0832V-167AC Cypress Semiconductor Corp, CY7C0832V-167AC Datasheet - Page 28

• Manufacturer Part Number: CY7C0832V-167AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C0832V-167AC

• Density: 4.5Mb
• Access Time (max): 4ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 167MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 18b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 300mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 120
• Word Size: 18b
• Number Of Words: 256K
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-06059 Rev. *K
Document History Page
Document Title: FLEx18
Document Number: 38-06059
REV.
*A
*B
*C
*D
*E
*G
*H
*K
*F
**
*J
*I
ECN NO.
122307
123636
126053
129443
231993
231813
111473
111942
113741
114704
115336
311054
See ECN
See ECN
See ECN
11/27/01
12/21/01
04/02/02
04/24/02
07/01/02
12/27/02
08/11/03
11/03/03
TM
1/27/03
Issue
Date
3.3V 32K/64K/128K/256K/512K x 18 Synchronous Dual-Port RAM
Change
Orig. of
WWZ
DSG
KRE
KRE
RYQ
KRE
KRE
SPN
RAZ
YDT
JFU
RBI
PRELIMINARY
Description of Change
Change from Spec number: 38-01056 to 38-06059
Updated capacitance values
Updated switching parameters and I
Updated “Read-to-Write-to-Read (OE Controlled)” waveform
Revised static discharge voltage
Revised footnote regarding I
Updated I
Updated ESD voltage
Corrected 0853 pins L3 and L12
Added discussion of Pause/Restart for JTAG boundary scan
Revised speed offerings for all densities
Power up requirements added to Maximum Ratings Information
Revise t
Separated out 4M and 9M data sheets
Updated I
Updated I
Removed “A particular port can write to a certain location while another port
is reading that location.” from Functional Description.
Removed x36 devices (CY7C0852/CY7C0851) from this datasheet. Added
0.5M, 1M and 9M x18 devices to it. Changed title to FLEx18 3.3V
32K/64K/128K/256K/512K x18 Synchronous Dual-Port RAM. Changed
datasheet to accommodate the removals and additions. Removed general
JTAG description. Updated JTAG ID codes for all devices. Added 144FBGA
package for all devices. Updated selection guide table and moved to the
front page. Updated block diagram to reflect x18 configuration. Added
preliminary status back due to the addition of the new devices.
Minor Change: Correct the revision indicated on the footer.
cd2
sb
sb
sb
, t
values
and I
and I
OE
, t
CC
CC
OHZ
values
values
, t
CKHZ
, t
SB3
CKLZ
CY7C0830V/CY7C0831V
CY7C0832V/CY7C0833V
for the CY7C0853V to 4.7 ns
SB3
CY7C0837V
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