CY7C1347B-166AC Cypress Semiconductor Corp, CY7C1347B-166AC Datasheet - Page 4

• Manufacturer Part Number: CY7C1347B-166AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1347B-166AC

• Density: 4Mb
• Access Time (max): 3.5ns
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Supply Current: 420mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.63V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Lead Free Status / Rohs Status: Not Compliant

Pin Definitions
A
BW
GW
BWE
CLK
CE
CE
CE
OE
ADV
ADSP
ADSC
ZZ
DQ
DP
V
V
V
V
MODE
NC
[16:0]
DD
SS
DDQ
SSQ
Name
1
2
3
[3:0]
[31:0]
[3:0]
Asynchronous
Asynchronous
Power Supply
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Input-Clock
I/O Ground
I/O Power
Ground
Supply
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Static
I/O-
I/O
Address Inputs used to select one of the 64K address locations. Sampled at the rising edge of the
CLK if ADSP or ADSC is active LOW, and CE
2-bit counter.
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global
write is conducted (ALL bytes are written, regardless of the values on BW
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a byte write.
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW,
the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input
data pins. OE is masked during the first clock of a read cycle when emerging from a deselected
state.
Advance Input signal, sampled on the rising edge of CLK. When asserted, it automatically incre-
ments the address in a burst cycle.
Address Strobe from Processor, sampled on the rising edge of CLK. When asserted LOW, A
is captured in the address registers. A
ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE
HIGH.
Address Strobe from Controller, sampled on the rising edge of CLK. When asserted LOW, A
is captured in the address registers. A
ADSC are both asserted, only ADSP is recognized.
ZZ “sleep” Input. This active HIGH input places the device in a non-time-critical “sleep” condition
with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin
has an internal pull-down.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by
the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
by A
OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQ
placed in a three-state condition.
Power supply inputs to the core of the device. Should be connected to 3.3V power supply.
Ground for the core of the device. Should be connected to ground of the system.
Power supply for the I/O circuitry. Should be connected to a 3.3V or 2.5V power supply.
Ground for the I/O circuitry. Should be connected to ground of the system.
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V
floating selects interleaved burst sequence. This is a strap pin and should remain static during
device operation. Mode Pin has an internal pull-up.
No Connects.
2
1
1
[16:0]
and CE
and CE
and CE
during the previous clock rise of the read cycle. The direction of the pins is controlled by
2
3
3
to select/deselect the device.
to select/deselect the device. ADSP is ignored if CE
to select/deselect the device.
4
[1:0]
[1:0]
are also loaded into the burst counter. When ADSP and
are also loaded into the burst counter. When ADSP and
Description
1
, CE
2
, and CE
3
are sampled active. A
1
is HIGH.
[3:0]
CY7C1347B
[31:0]
and BWE).
1
is deasserted
and DP
[1:0]
DDQ
feed the
[3:0]
or left
[16:0]
[16:0]
are