CY7C4245V-15ASC Cypress Semiconductor Corp, CY7C4245V-15ASC Datasheet - Page 15

CY7C4245V-15ASC

Manufacturer Part Number
CY7C4245V-15ASC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C4245V-15ASC

Configuration
Dual
Density
64Kb
Access Time (max)
11ns
Word Size
18b
Organization
4Kx18
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
TQFP
Clock Freq (max)
66.7MHz
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Supply Current
30mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
64
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C4245V-15ASC
Manufacturer:
CYPRESS
Quantity:
1 831
Part Number:
CY7C4245V-15ASC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Document #: 38-06029 Rev. *C
Switching Waveforms
Programmable Almost Full Flag Timing
Programmable Almost Full Flag Timing (applies only in SMODE (SMODE in LOW))
Notes:
24. PAF offset = m. Number of data words written into FIFO already = 64 − m + 1 for the CY7C4425V, 256 − m + 1 for the CY7C4205V, 512 − m + 1 for the CY7C4215V.
25. PAF is offset = m.
26. 64 − m words in CY7C4425V, 256 – m words inCY7C4205V, 512 − m words in CY7C4215V. 1024 – m words in CY7C4225V, 2048 − m words in CY7C4235V,
27. 64 − m + 1 words in CY7C4425V, 256 − m + 1 words in CY7C4205V, 512 − m +1 words in CY7C4215V, 1024 − m + 1 CY7C4225V, 2048 − m + 1 in CY74235V,
28. If a write is performed on this rising edge of the write clock, there will be Full – (m–1) words of the FIFO when PAF goes LOW.
29. PAF offset = m.
30. t
1024 − m + 1 for the CY7C4225V, 2048 − m + 1 for the CY7C4235V, and 4096 − m + 1 for the CY7C4245V.
and 4096 – m words in CY7C4245V.
and 4096 − m + 1 words in CY7C4245V.
RCLK and the rising edge of WCLK is less than t
SKEW3
RCLK
WCLK
WCLK
PAF
RCLK
WEN
WEN
REN
REN
PAF
is the minimum time between a rising RCLK and a rising WCLK edge for PAF to change state during that clock cycle. If the time between the edge of
[25]
t
CLKH
FULL – (M + 1) WORDS
(continued)
IN FIFO
t
CLKH
t
ENS
SKEW3
t
ENH
, then PAF may not change state until the next WCLK rising edge.
t
CLKL
Note 24
Note 29
Note 28
t
ENS
t
ENH
t
CLKL
t
PAF
t
PAF
t
ENS
t
ENS
FULL − M WORDS
t
SKEW3
FULL − M WORDS
CY7C4225V/4205V/4215V
CY7C4425V/4235V/4245V
IN FIFO
IN FIFO
[30]
t
ENS
[26]
t
PAF
t
[26]
ENH
FULL − (M + 1) WORDS
t
IN FIFO
PAFsynch
Page 15 of 20
[27]

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