CY7C67300-100AI Cypress Semiconductor Corp, CY7C67300-100AI Datasheet - Page 25

• Manufacturer Part Number: CY7C67300-100AI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C67300-100AI

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: TQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

External Memory Control Register [0xC03A] [R/W]
Table 38. External Memory Control Register
Register Description
The External Memory Control register provides control of Wait
States for the external SRAM or ROM. All wait states are based
off of 48 MHz.
XRAM Merge Enable (Bit 13)
The XRAM Merge Enable bit enables or disables the RAM merge
feature. When the RAM merge feature is enabled, the
nXRAMSEL is active whenever the nXMEMSEL is active.
1: Enable RAM merge
0: Disable RAM merge
XROM Merge Enable (Bit 12)
The XROM Merge Enable bit enables or disables the ROM
merge feature. When the ROM merge feature is enabled, the
nXROMSEL is active whenever the nXMEMSEL is active.
1: Enable ROM merge
0: Disable ROM merge
XMEM Width Select (Bit 11)
The XMEM Width Select bit selects the extended memory width.
1: Extended memory = 8
0: Extended memory = 16
XMEM Wait Select (Bits [10:8])
The XMEM Wait Select field selects the extended memory wait
state from 0 to 7.
XROM Width Select (Bit 7)
The XROM Width Select bit selects the external ROM width.
1: External memory = 8
0: External memory = 16
Document #: 38-08015 Rev. *J
Bit #
Field
Read/Write
Default
Bit #
Field
Read/Write
Default
XROM Width
Select
R/W
15
X
X
7
-
Reserved
R/W
14
X
X
6
-
XRAM Merge
XROM Wait
Enable
Select
R/W
R/W
13
X
X
5
XROM Merge
Enable
R/W
R/W
12
X
X
4
XROM Wait Select (Bits[6:4])
The XROM Wait Select field selects the external ROM wait state
from 0 to 7.
XRAM Width Select (Bit 3)
The XRAM Width Select bit selects the external RAM width.
1: External memory = 8
0: External memory = 16
XRAM Wait Select (Bits[2:0])
The XRAM Wait Select field selects the external RAM wait state
from 0 to 7.
Reserved
Write all reserved bits with ’0’.
Timer Registers
There are three registers dedicated to timer operations. Each of
these registers are discussed in this section and are summarized
in
Table 39. Timer Registers
Watchdog Timer Register
Timer 0 Register
Timer 1 Register
Table
XMEM Width
XRAM Width
Select
Select
Register Name
R/W
R/W
39.
11
X
X
3
R/W
R/W
10
X
X
2
XRAM Wait
XMEM Wait
Address
0xC00C
0xC010
0xC012
Select
Select
R/W
R/W
X
1
9
X
CY7C67300
Page 25 of 99
R/W
R/W
X
0
X
8
R/W
R/W
R/W
R/W
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