CY7C68013-128AC Cypress Semiconductor Corp, CY7C68013-128AC Datasheet - Page 34

• Manufacturer Part Number: CY7C68013-128AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C68013-128AC

• Cpu Family: FX2LP
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 48MHz
• Interface Type: I2C/USB
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Total Internal Ram Size: 8KB
• # I/os (max): 40
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 128
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

9.6
Table 9-5. Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK
Table 9-6. Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK
Document #: 38-08012 Rev. *F
t
t
t
t
t
t
t
t
t
t
t
t
t
t
IFCLK
SRD
RDH
OEon
OEoff
XFLG
XFD
IFCLK
SRD
RDH
OEon
OEoff
XFLG
XFD
Parameter
Parameter
Slave FIFO Synchronous Read
IFCLK Period
SLRD to Clock Set-up Time
Clock to SLRD Hold Time
SLOE Turn-on to FIFO Data Valid
SLOE Turn-off to FIFO Data Hold
Clock to FLAGS Output Propagation Delay
Clock to FIFO Data Output Propagation Delay
IFCLK Period
SLRD to Clock Set-up Time
Clock to SLRD Hold Time
SLOE Turn-on to FIFO Data Valid
SLOE Turn-off to FIFO Data Hold
Clock to FLAGS Output Propagation Delay
Clock to FIFO Data Output Propagation Delay
FLAGS
DATA
SLOE
SLRD
IFCLK
Figure 9-5. Slave FIFO Synchronous Read Timing Diagram
Description
Description
t
OEon
N
t
SRD
t
IFCLK
t
RDH
t
XFLG
t
XFD
N+1
20.83
20.83
Min.
18.7
Min.
12.7
3.7
t
0
OEoff
[15]
[15]
[13]
Max.
Max.
10.5
10.5
10.5
10.5
13.5
200
9.5
11
15
CY7C68013
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Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns