W77C32F-40 Nuvoton Technology Corporation of America, W77C32F-40 Datasheet
W77C32F-40
Specifications of W77C32F-40
Related parts for W77C32F-40
W77C32F-40 Summary of contents
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Table of Content- 1. GENERAL DESCRIPTION ......................................................................................................... 3 2. FEATURES ................................................................................................................................. 3 3. PIN CONFIGURATIONS ............................................................................................................ 4 4. PIN DESCRIPTION..................................................................................................................... 5 5. BLOCK DIAGRAM ...................................................................................................................... 6 6. FUNCTIONAL DESCRIPTION ................................................................................................... 7 7. MEMORY ORGANIZATION ....................................................................................................... 9 7.1 Program Memory ............................................................................................................ ...
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Time-base Selection ...............................................................................................52 13.1.2 Mode 0....................................................................................................................53 13.1.3 Mode 1....................................................................................................................53 13.1.4 Mode 2....................................................................................................................53 13.1.5 Mode 3....................................................................................................................54 13.2 Timer/Counter 2............................................................................................................ 55 13.2.1 Capture Mode.........................................................................................................55 13.2.2 Auto-reload Mode, Counting Up .............................................................................55 13.2.3 Auto-reload Mode, Counting Up/Down ...................................................................56 13.2.4 Baud Rate Generator Mode....................................................................................57 ...
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... Software programmable access cycle to external RAM/peripherals • Packages: − DIP 40: W77C32-40 − PLCC 44: W77C32P-40 − QFP 44: W77C32F-40 − Lead Free (RoHS) DIP 40: − Lead Free (RoHS) PLCC 44: − Lead Free (RoHS) PQFP 44: W77C32/W77C032 W77C032A40DL W77C032A40PL W77C032A40FL Publication Release Date: December 20, 2005 ...
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... PSEN 13 28 P2.7, A15 INT1, P3.3 14 T0, P3.4 27 P2.6, A14 15 T1, P3.5 26 P2.5, A13 16 WR, P3.6 25 P2.4, A12 17 24 P2.3, A11 RD, P3.7 18 XTAL2 23 P2.2, A10 19 XTAL1 22 P2. VSS 21 P2.0, A8 44-Pin QFP (W77C32F INT3, P1.5 P0.4, AD4 39 INT4, P1.6 38 P0.5, AD5 37 INT5, P1.7 P0 ...
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PIN DESCRIPTION SYMBOL TYPE I EXTERNAL ACCESS ENABLE: It should be kept low. EA PROGRAM STORE ENABLE: PSEN enables the external ROM data onto the O PSEN Port 0 address/data bus during fetch and MOVC operations. ADDRESS LATCH ENABLE: ...
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BLOCK DIAGRAM P1.0 ∫ Port Port 1 1 Latch P1.7 Interrupt Timer 2 Timer 0 Timer 1 2 UARTs Port 3 Port P3.0 Latch 3 ∫ P3.7 Port 4 Latch P4.0 Port ∫ 4 Oscillator P4.3 XTAL1 ACC B ...
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FUNCTIONAL DESCRIPTION The W77C32 is 8052 pin compatible and instruction set compatible. It includes the resources of the standard 8052 such as four 8-bit I/O Ports, three 16-bit timer/counters, full duplex serial port and interrupt sources. The W77C32 features ...
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Timers The W77C32 has three 16-bit timers that are functionally similar to the timers of the 8052 family. When used as timers, they can be set to run at either 4 clocks or 12 clocks per count, thus providing the ...
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MEMORY ORGANIZATION The W77C32 separates the memory into two separate sections, the Program Memory and the Data Memory. The Program Memory is used to store the instruction op-codes, while the Data Memory is used to store data or for ...
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FFh Indirect RAM 80h 7Fh Direct RAM 30h 2Fh 2Eh 2Dh 2Ch 2Bh 2Ah 29h 4F ...
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SPECIAL FUNCTION REGISTERS The W77C32 uses Special Function Registers (SFRs) to control and monitor peripherals and their Modes. The SFRs reside in the register locations 80-FFh and are accessed by direct addressing only. Some of the SFRs are bit ...
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Port open-drain bi-directional I/O port. This port also provides a multiplexed low order address/data bus during accesses to external memory. Stack Pointer Bit: SP.7 Mnemonic: SP The Stack Pointer stores the Scratchpad RAM address where the stack ...
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This is the high byte of the new additional 16-bit data pointer that has been added to the W77C32. The user can switch between DPL, DPH and DPL1, DPH1 simply by setting register DPS = 1. The instructions that use ...
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IE1: Interrupt 1 edge detect: Set by hardware when an edge/level is detected on INT1 . This bit is cleared by hardware when the service routine is vectored to only if the interrupt was edge triggered. Otherwise it follows the ...
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Timer 1 LSB Bit: TL1.7 Mnemonic: TL1 TL1.7-0: Timer 1 LSB Timer 0 MSB Bit: TH0.7 Mnemonic: TH0 TH0.7-0: Timer 0 MSB Timer 1 MSB Bit: TH1.7 Mnemonic: TH1 TH1.7-0: Timer 1 MSB Clock Control Bit: WD1 Mnemonic: CKCON WD1-0: ...
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MD2-0: Stretch MOVX select bits: These three bits are used to select the stretch value for the MOVX instruction. Using a variable MOVX length enables the user to access slower external memory devices or peripherals without the need for external ...
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External Interrupt Flag Bit: IE5 Mnemonic: EXIF IE5: External Interrupt 5 flag. Set by hardware when a falling edge is detected on INT5 . IE4: External Interrupt 4 flag. Set by hardware when a rising edge is detected on ...
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SM2: Multiple processors communication. Setting this bit to 1 enables the multiprocessor communication feature in mode 2 and 3. In mode SM2 is set to 1, then RI will not be activated if the received 9th ...
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Interrupt Enable Bit: EA Mnemonic: IE EA: Global enable. Enable/disable all interrupts. ES1: Enable Serial Port 1 interrupt. ET2: Enable Timer 2 interrupt. ES: Enable Serial Port 0 interrupt. ET1: Enable Timer 1 interrupt EX1: Enable external interrupt 1 ET0: ...
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P3.7-0: General purpose I/O port. Each pin also has an alternate input or output function. The alternate functions are described below. P3.7 RD Strobe for read from external RAM P3.6 WR Strobe for write to external RAM P3.5 T1 Timer/counter ...
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This register enables the Automatic Address Recognition feature of the Serial port 1. When all the bits of SADEN1 are 0, interrupt will occur for any incoming address. Serial Port Control 1 Bit: 7 SM0_1/FE_1 Mnemonic: SCON1 SM0_1/FE_1: Serial ...
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SBUF1.7-0: Serial data of the serial port 1 is read from or written to this location. It actually consists of two separate 8-bit registers. One is the receive resister, and the other is the transmit buffer. Any read access gets ...
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Status Register Bit HIP Mnemonic: STATUS HIP: High Priority Interrupt Status. When set, it indicates that software is servicing a high priority interrupt. This bit will be cleared when the program executes the corresponding RETI instruction. LIP: ...
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TF2: Timer 2 overflow flag: This bit is set when Timer 2 overflows also set when the count is equal to the capture register in down count mode. It can be set only if RCLK and TCLK are ...
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T2CR: Timer 2 Capture Reset. In the Timer 2 Capture Mode this bit enables/disables hardware automatically reset Timer 2 while the value in TL2 and TH2 have been transferred into the capture register. T2OE: Timer 2 Output Enable. This bit ...
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CY: Carry flag: Set for an arithmetic operation which results in a carry being generated from the ALU also used as the accumulator for the bit operations. AC: Auxiliary carry: Set when the previous operation resulted in a ...
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Accumulator Bit: 7 ACC.7 Mnemonic: ACC ACC.7-0: The A (or ACC) register is the standard 8052 accumulator. Extended Interrupt Enable Bit Mnemonic: EIE EIE.7-5: Reserved bits, will read high EWDI: Enable Watchdog timer interrupt EX5: External Interrupt 5 ...
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INSTRUCTION The W77C32 executes all the instructions of the standard 8032 family. The operation of these instructions, their effect on the flag bits and the status bits is exactly the same. However, timing of these instructions is different. The ...
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Table 3. Instruction Timing for W77C32, continued HEX Instruction Op-Code ADDC ADDC A, @R0 36 ADDC A, @R1 37 ADDC A, direct 35 ADDC A, #data 34 71, 91, B1, 11, ACALL addr11 31, 51, D1, F1 ...
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Table 3. Instruction Timing for W77C32, continued HEX Instruction Op-Code DEC R3 1B DEC R4 1C DEC R5 1D DEC R6 1E DEC R7 1F DEC @R0 16 DEC @R1 17 DEC direct 15 DEC DPTR A5 DIV AB 84 ...
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Table 3. Instruction Timing for W77C32, continued HEX Instruction Op-Code JNB bit, rel 30 JBC bit, rel 10 LCALL addr16 12 LJMP addr16 02 MUL AB A4 MOV MOV MOV MOV ...
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Table 3. Instruction Timing for W77C32, continued HEX Instruction Op-Code MOV @R0, direct A6 MOV @R1, direct A7 MOV @R0, #data 76 MOV @R1, #data 77 MOV direct MOV direct MOV direct MOV direct, ...
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Table 3. Instruction Timing for W77C32, continued HEX Instruction Op-Code ORL A, direct 45 ORL A, #data 44 ORL direct ORL direct, #data 43 ORL C, bit 72 ORL C, /bit A0 PUSH direct C0 POP direct D0 ...
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Table 3. Instruction Timing for W77C32, continued HEX Instruction Op-Code XCH A, @R0 C6 XCH A, @R1 C7 XCHD A, @R0 D6 XCHD A, @R1 D7 XCH A, direct C5 XRL XRL XRL A, ...
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Instruction Timing The instruction timing for the W77C32 is an important aspect, especially for those users who wish to use software instructions to generate timing delays. Also, it provides the user with an insight into the timing differences between ...
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Instruction Fetch C1 C2 CLK ALE PSEN PC AD7-0 PORT 2 Figure 4: Two Cycle Instruction Timing Instruction Fetch CLK ALE PSEN A7-0 OP-CODE AD7-0 PORT 2 Address A15-8 Figure 5: Three Cycle Instruction Timing Instruction Fetch ...
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Instruction Fetch Operand Fetch CLK ALE PSEN OP-CODE AD7-0 A7-0 Address A15-8 PORT 2 9.2 MOVX Instruction The W77C32, like the standard 8032, uses the MOVX instruction to access external Data Memory. This Data Memory ...
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MOV R2, #CNT ; Load R2 with the count value MOV R3, #SL ; Save low byte of Source Address in R3 MOV R4, #SH ; Save high byte of Source address in R4 MOV R5, #DL ; Save low ...
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If CNT = 50 Clock cycles in W77C32 = (12 + ( (12 + 750 3048 We can see that in the first program the standard 8032 takes 15720 cycles, while the ...
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Last Cycle of Previous Instruction CLK ALE PSEN WR A0-A7 D0-D7 PORT 0 MOVX Inst. Address MOVX Inst PORT 2 A15-A8 Figure 8: Data Memory Write with Stretch Value = 0 Last Cycle of Previous ...
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Last Cycle of Previous Instruction CLK ALE PSEN WR A0-A7 D0-D7 PORT 0 MOVX Inst. Address MOVX Inst. PORT 2 A15-A8 Figure 10: Dada Memory Write with Stretch Value = 2 9.4 Wait State Control Signal ...
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Wait State Control Signal Timing ( when Stretch = 1 ) First Machine Cycle CLOCK ALE PSEN ADDRESS WAIT Wait State Control Signal Timing ( when Stretch = 2 ) First Machine Cycle ...
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POWER MANAGEMENT The W77C32 has several features that help the user to modify the power consumption of the device. The power saving features are basically the POWER DOWN mode, ECONOMY mode and the IDLE mode of operation. 10.1 Idle ...
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The selection of instruction rate is going to take effect after a delay of one instruction cycle. Switching to divide 1024 mode must first go from divide by 4 mode. This means software can not switch directly ...
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The W77C32 can be woken from the Power Down mode by forcing an external interrupt pin activated, provided the corresponding interrupt is enabled, while the global enable(EA) bit is set and the external input has been set to a level ...
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RESET CONDITIONS The user has several hardware related options for placing the W77C32 into reset condition. In general, most register bits go to their reset value irrespective of the reset condition, but there are a few flags whose state ...
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Table 6. SFR Reset Value SFR NAME P0 SP DPL DPH DPL1 DPH1 DPS PCON TCON TMOD TL0 TL1 TH0 TH1 CKCON P1 SCON SBUF P2 SADDR1 SCON1 ROMMAP EXIF P4 The WDCON SFR bits are set/cleared in reset condition ...
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INTERRUPTS The W77C32 has a two priority level interrupt structure with 12 interrupt sources. Each of the interrupt sources has an individual priority bit, flag, interrupt vector and enable bit. In addition, the interrupts can be globally enabled or ...
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Priority Level Structure There are two priority levels for the interrupts, high and low. The interrupt source can be individually set to either high or low levels. Naturally, a higher priority interrupt cannot be interrupted by a lower priority ...
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The processor responds to a valid interrupt by executing an LCALL instruction to the appropriate service routine. This may or may not clear the flag which caused the interrupt. In case of Timer interrupts, the TF0 or TF1 flags are ...
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A longer response time should be anticipated if any of the three conditions are not met higher or equal priority is being serviced, then the interrupt latency time obviously depends on the nature of the service routine currently ...
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PROGRAMMABLE TIMERS/COUNTERS The W77C32 has three 16-bit programmable timer/counters and one programmable Watchdog timer. The Watchdog timer is operationally quite different from the other two timers. 13.1 Timer/Counters 0 & 1 The W77C32 has two 16-bit Timer/Counters. Each of ...
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Mode 0 In Mode 0, the timer/counters act bit counter with a 5 bit, divide by 32 pre-scale. In this mode we have a 13 bit timer/counter. The 13 bit counter consists of 8 bits of ...
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T0M = CKCON.3 (T1M = CKCON.4) Clock Source Mode input 1/4 div osc/1 div osc/16 div. by 1024 osc/256 1/ P3.4 (T1 = P3.5) TR0 = TCON.4 (TR1 = TCON.6) GATE = TMOD.3 (GATE ...
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Timer/Counter 2 Timer/Counter bit up/down counter which is configured by the T2MOD register and controlled by the T2CON register. Timer/Counter 2 is equipped with a capture/reload capability. As with the Timer 0 and Timer 1 ...
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T2M = CKCON.5 Clock Source 1/4 Mode input div osc/1 div osc/16 div. by 1024 osc/256 1/ P1.0 TR2 = T2CON.2 T2EX = P1.1 EXEN2 = T2CON.3 13.2.3 Auto-reload Mode, Counting Up/Down Timer/Counter 2 ...
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Baud Rate Generator Mode The baud rate generator mode is enabled by setting either the RCLK or TCLK bits in T2CON register. While in the baud rate generator mode, Timer/Counter bit counter with auto reload ...
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WATCHDOG TIMER The Watchdog timer is a free-running timer which can be programmed by the user to serve as a system monitor, a time-base generator or an event timer basically a set of dividers that divide the ...
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The watchdog time-out selection will result in different time-out values depending on the clock speed. The reset, when enabled, will occur 512 clocks after the time-out has occurred. Table 9. Time-out values for the Watchdog timer WATCHDOGI WD1 WD0 NTERVAL ...
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SERIAL PORT Serial port in the W77C32 is a full duplex port. The W77C32 provides the user with additional features such as the Frame Error Detection and the Automatic Address Recognition. The serial ports are capable of synchronous as ...
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The TI flag is set high in C1 following the end of transmission of the last bit. The serial port will receive data when REN is 1 and RI is zero. The shift clock (TxD) will be activated and the ...
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Timer 1 Timer 2 Overflow Overflow (for Serial Port 0 only) ÷ ≠ SMOD (SMOD_1) TCLK 0 1 ÷ Φ RCLK 0 1 ÷ Φ⎧ SAMPLE 1-TO-0 DETECTOR RXD Mode 2 ...
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Either SM2 = 0, or the received stop bit = 1. If these conditions are met, then the stop bit goes to RB8, the 8 data bits go into SBUF and RI is set. Otherwise the received frame may ...
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Timer 1 Timer 2 Overflow Overflow (for Serial Port 0 only) ÷2 SMOD (SMOD_1) TCLK 0 1 ÷16 RCLK 0 1 ÷16 SAMPLE 1-TO-0 DETECTOR RXD Framing Error Detection A Frame Error occurs when a valid stop bit ...
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All the slave processors should have their SM2 bit set high when waiting for an address byte. This ensures that ...
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TIMED ACCESS PROTECTION The W77C32 has several new features, like the Watchdog timer, on-chip ROM size adjustment, wait state control signal and Power on/fail reset flag, which are crucial to proper operation of the system. If left unprotected, errant ...
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Example 4: Invalid Access MOV TA, #0AAh 3 M/C NOP 1 M/C MOV TA, #055h 3 M/C SETB EWT 2 M/C In the first two examples, the writing to the protected bits is done before the 3 machine cycle window ...
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ELECTRICAL CHARACTERISTICS 17.1 Absolute Maximum Ratings PARAMETER DC Power Supply Input Voltage Operating Temperature Storage Temperatute Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. 17.2 D.C. ...
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DC Characteristics, continued PARAMETER Input High Voltage P0, P1, P2, P3, EA Input High Voltage RST Input High Voltage [*3] XTAL1 Output Low Voltage P1, P2, P3 Output Low Voltage [*2] P0, ALE, PSEN Output High Voltage P1, P2, P3 ...
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A.C. Characteristics 17.3.1 External Clock Characteristics PARAMETER Clock High Time Clock Low Time Clock Rise Time Clock Fall Time Note: Duty cycle 17.3.2 A.C. Specification PARAMETER Oscillator Frequency ALE Pulse Width Address Valid to ALE Low ...
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MOVX Characteristics Using Stretch Memory Cycles PARAMETER Data Access ALE Pulse Width Address Hold After ALE Low for MOVX Write RD Pulse Width WR Pulse Width RD Low to Valid Data In Data Hold after Read Data Float after ...
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17.3.4 Explanation of Logic Symbols In order to maintain compatibility with the original 8051 family, this device specifies the same parameter for ...
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TIMING WAVEFORMS 18.1 Program Memory Read Cycle t LHLL ALE t AVLL PSEN ADDRESS PORT 0 PORT 2 18.2 Data Memory Read Cycle ALE PSEN RD PORT 0 INSTRUCTION IN PORT 2 t LLIV t PLPH t PLIV t ...
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Timing Waveforms, continued 18.3 Data Memory Write Cycle ALE PSEN WR INSTRUCTION PORT 0 IN PORT 2 t LLWL t WLWH t LLAX2 t AVLL t AVWL1 t QVWX ADDRESS DATA OUT A0-A7 t AVDV2 ADDRESS A8-A15 - 74 - ...
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TYPICAL APPLICATION CIRCUITS 19.1 Expanded External Program Memory and Crystal XTAL1 XTAL2 CRYSTAL 8 RST C1 C2 INT0 12 13 INT1 P1.0 2 ...
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Typical Application Circuits, continued 19.2 Expanded External Data Memory and Oscillator XTAL1 10 u OSCILLATOR 18 XTAL2 8 RST INT0 12 13 INT1 P1.0 2 P1.1 3 P1.2 ...
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PACKAGE DIMENSIONS 20.1 40-pin DIP W77C32/W77C032 Symbol 21 20 Notes Dimension D Max. & S include mold flas c 2. Dimension E1 ...
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Package Dimensions, continued 20.2 44-pin PLCC θ Seating Plane 20.3 44-pin QFP See ...
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REVISION HISTORY VERSION DATE A2 July, 2001 A3 June, 2004 A4 April 18, 2005 A5 December 20, 2005 Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, ...