W77C32F-40 Nuvoton Technology Corporation of America, W77C32F-40 Datasheet - Page 22

• Manufacturer Part Number: W77C32F-40
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W77C32F-40

• Lead Free Status / Rohs Status: Supplier Unconfirmed

SBUF1.7-0: Serial data of the serial port 1 is read from or written to this location. It actually consists of
ROMMAP
WS:
Power Management Register
CD1, CD0: Clock Divide Control. These bit selects the number of clocks required to generate one
SWB:
XTOFF: Crystal Oscillator Disable. Setting this bit disables the external crystal oscillator. This bit can
ALEOFF: This bit disables the expression of the ALE signal on the device pin during all on-board
DME0:
Bit:
Switchback Enable. Setting this bit allows an enabled external interrupt or serial port activity
to force the CD1,CD0 to divide by 4 state (0,1). The device will switch modes at the start of
the jump to interrupt service routine while a external interrupt is enabled and actually
recongnized by microcontroller. While a serial port reception, the switchback occurs at the
start of the instruction following the falling edge of the start bit.
only be set to 1 while the microcontroller is operating from the RC oscillator. Clearing this bit
restarts the crystal oscillator, the XTUP (STATUS.4) bit will be set after crystal oscillator
warmed-up has completed.
This bit determines the on-chip MOVX SRAM to be enabled or disabled.
Set this bit to 1 will enable the on-chip 1KB MOVX SRAM.
0 = ALE expression is enable;
program and data memory accesses. External memory accesses will automatically enable
ALE independent of ALEOFF.
machine cycle. There are three modes including divide by 4, 64 or 1024. Switching
between modes must first go back devide by 4 mode. For instance, to go from 64 to 1024
clocks/machine cycle the device must first go from 64 to 4 clocks/machine cycle, and then
from 4 to 1024 clocks/machine cycle.
two separate 8-bit registers. One is the receive resister, and the other is the transmit
buffer. Any read access gets data from the receive data buffer, while write accesses are
to the transmit data buffer.
CD1,
Mnemonic: ROMMAP
Mnemonic: PMR
Wait State Signal Enable. Setting this bit enables the WAIT signal on P4.0. The
device will sample the wait state control signal WAIT via P4.0 during MOVX
instruction. This bit is time access protected
0
0
1
1
CD1
7
Bit:
CD0
0
1
0
1
CD0
WS
7
6
Clocks/machine cycle
SWB
6
1
5
Reserved
4
64
1024
1 = ALE expression is disable
5
4
-
-
- 22 -
XTOFF
4
-
3
ALE-OFF
3
-
2
W77C32/W77C032
Address: C2h
Address: C4h
2
-
1
-
1
-
DME0
0
0
-