CAT25C64S-TE13 ON Semiconductor, CAT25C64S-TE13 Datasheet
CAT25C64S-TE13
Specifications of CAT25C64S-TE13
Related parts for CAT25C64S-TE13
CAT25C64S-TE13 Summary of contents
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... Self-timed write cycle 8-pin DIP/SOIC and 14-pin TSSOP 64-Byte page write buffer Block write protection – Protect 1/4, 1/2 or all of EEPROM array required to access the device. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. The CAT25C32/64 is designed with software and hardware write protection features including Block write protection ...
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CAT25C32/64 ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias ................. – +125 C Storage Temperature ....................... – +150 C Voltage on any Pin with 1) Respect to V ................... –2. with Respect to V ...
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PIN CAPACITANCE Applicable over recommended operating range from T Symbol Test Conditions C Output Capacitance (SO) OUT Input Capacitance (CS, SCK, SI, WP, HOLD A.C. CHARACTERISTICS SYMBOL PARAMETER t Data Setup Time SU t Data Hold Time ...
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CAT25C32/64 FUNCTIONAL DESCRIPTION The CAT25C32/64 supports the SPI bus data transmission protocol. The synchronous Serial Peripheral Interface (SPI) helps the CAT25C32/64 to interface directly with many of today’s popular microcontrollers. The CAT25C32/64 contains an 8-bit instruction register. (The instruction set ...
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Opcodes, byte addresses, or data present on the SI pin are latched on the rising edge of the SCK. Data on the SO pin is updated on the falling edge of the ...
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CAT25C32/64 STATUS REGISTER The Status Register indicates the status of the device. The RDY (Ready) bit indicates whether the CAT25C32 busy with a write operation. When set write cycle is in progress and when set ...
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READ Sequence The part is selected by pulling CS low. The 8-bit read instruction is transmitted to the CAT25C32/64, fol- lowed by the 16-bit address(the three Most Significant Bits are don’t care for 25C64 and four most significant bits are ...
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CAT25C32/64 Byte Write Once the device Write Enable state, the user may proceed with a write sequence by setting the CS low, issuing a write instruction via the SI line, followed by the 16-bit address (the three ...
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Access to the array during an internal write cycle is ignored and program-ming is continued. On power up high impedance. Figure 8. Page Write Instruction ...
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CAT25C32/64 ORDERING INFORMATION Prefix Device # 25C64 CAT Product Optional Number Company ID 25C32: 32K 25C64: 64K Package P: PDIP S: SOIC U14: 14-pin TSSOP L: PDIP (Lead free, Halogen free) V: SOIC, JEDEC (Lead free, Halogen free) Y14: 14-pin ...
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REVISION HISTORY Date Rev. Reason 8/4/2004 F Updated Features Updated DC Operating Characteristics table & notes 03/29/05 G Update Reliability Characteristics Update Instruction Set - Power-Up Timing 07/08/05 H Update Features Update Pin Configuation Update Ordering Information 09/22/05 I Update ...