W39V040FAP Winbond Electronics, W39V040FAP Datasheet - Page 12

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W39V040FAP

Manufacturer Part Number
W39V040FAP
Description
Manufacturer
Winbond Electronics
Datasheet

Specifications of W39V040FAP

Density
4Mb
Access Time (max)
150ns
Interface Type
Parallel/Serial
Boot Type
Top
Address Bus
4/11Bit
Operating Supply Voltage (typ)
3/3.3V
Operating Temp Range
0C to 70C
Package Type
PLCC
Program/erase Volt (typ)
3.3V
Sync/async
Async/Sync
Operating Temperature Classification
Commercial
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Word Size
8b
Number Of Words
512K
Supply Current
20mA
Mounting
Surface Mount
Pin Count
32
Lead Free Status / Rohs Status
Not Compliant

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6.19 FWH Cycle Definition
START
IDSEL
MSIZE
TAR
ADDR
SYNC
DATA
FIELD
CLOCKS
NO. OF
N
1
1
1
2
7
2
"1101b" indicates FWH Memory Read cycle; while "1110b" indicates FWH
Memory Write cycle. 0000b" appears on FWH bus to indicate the initial
This one clock field indicates which FWH component is being selected.
Memory Size. There is always show “0000b” for single byte access.
Turned Around Time
Address Phase for Memory Cycle. FWH supports the 28 bits address
protocol. The addresses transfer most significant nibble first and least
significant nibble last. (i.e. Address[27:24] on FWH[3:0] first, and
Address[3:0] on FWH[3:0] last.)
Synchronous to add wait state. "0000b" means Ready, "0101b" means
Short Wait, "0110b" means Long Wait, "1001b" for DMA only, "1010b"
means error, and other values are reserved.
Data Phase for Memory Cycle. The data transfer least significant nibble
first and most significant nibble last. (i.e. DQ[3:0] on FWH[3:0] first, then
DQ[7:4] on FWH[3:0] last.)
- 12 -
DESCRIPTION
W39V040FA

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