ACS8510 Semtech, ACS8510 Datasheet
ACS8510
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ACS8510 Summary of contents
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... PDH network, and node synchronization. The ACS8510 generates independent SEC and BITS clocks kHz Frame Synchronization clock and a 2 kHz Multi-Frame Synchronization clock. Two ACS8510 devices can be used together in a Master/Slave configuration mode allowing sys- tem protection against a single ACS8510 failure. A microprocessor port is incorporated, providing access to the configuration and status registers for device setup and monitoring ...
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... Pre-Locked(2) mode ........................................................................................................................................................................ 42 Protection Facility ........................................................................................................................................................................................ 43 Alignment of Priority Tables in Master and Slave ACS8510 ................................................................................................. 44 Alignment of the Selection of Reference Sources for TOUT4 Generation in the Master and Slave ACS8510 ........... 45 Alignment of the Phases of the 8kHz and 2kHz Clocks in both Master and Slave ACS8510 ....................................... 45 JTAG .................................................................................................................................................................................................................. 45 PORB ................................................................................................................................................................................................................ 45 Electrical Specification .......................................................................................................................................................................... 48 Revision 2 ...
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... List of Figures List of Figures List of Figures Figure 1. Simple Block Diagram ............................................................................................................................................................. 1 Figure 2. ACS8510 Pin Diagram ............................................................................................................................................................ 5 Figure 3. Minimum Input Jitter Tolerance (OC-3/STM-1) ................................................................................................................... 15 Figure 4. Minimum Input Jitter Tolerance (DS1/E1) .......................................................................................................................... 16 Figure 5. Wander and Jitter Measured Transfer Characteristics ....................................................................................................... 18 Figure 6. Maximum Time Interval Error of TOUT0 output port ........................................................................................................... 20 Figure 7 ...
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... Table 39. Write Access Timing in SERIAL Mode (for use with Figure 26) ........................................................................................ 70 Table 40. Access Timing in EPROM Mode (for use with Figure 27) .................................................................................................. 71 Table 41. 100 Pin LQFP Package Dimension Data (for use with Figure 28) ................................................................................... 73 Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS 4 FINAL www.semtech.com ...
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... ADVANCED COMMUNICATIONS Pin Diagram Pin Diagram Pin Diagram Pin Diagram Pin Diagram Figure 2. ACS8510 Pin Diagram Figure 2. ACS8510 Pin Diagram Figure 2. ACS8510 Pin Diagram Figure 2. ACS8510 Pin Diagram Figure 2. ACS8510 Pin Diagram 1 AGND 2 TRST AGND 6 VA1+ 7 TMS 8 INTREQ 9 TCK 10 REFCLK 11 DGND ...
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... Table 1. Power Pins Table 1. Power Pins Table 1. Power Pins Table 1. Power Pins Table 1. Power Pins Table 2. No Connections Table 2. No Connections Table 2. No Connections Table 2. No Connections Table 2. No Connections Note input output power, TTL Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS ...
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... ADVANCED COMMUNICATIONS Table 3. Other Pins Table 3. Other Pins Table 3. Other Pins Table 3. Other Pins Table 3. Other Pins Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS FINAL / / / / www.semtech.com ...
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... ADVANCED COMMUNICATIONS Table 3. Other Pins (continued) Table 3. Other Pins (continued) Table 3. Other Pins (continued) Table 3. Other Pins (continued) Table 3. Other Pins (continued Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS FINAL / / / / www.semtech.com ...
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... Network Element, for the generation of SEC and frame synchronization pulses. In Free-run mode, the ACS8510 generates a stable, low- noise clock signal from an internal oscillator. In Locked mode, the ACS8510 selects the most appropriate input reference source and generates a stable, low-noise clock signal locked to the selected reference. In Holdover mode, ...
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... Input Interfaces Input Interfaces Input Interfaces Input Interfaces Input Interfaces The ACS8510 supports up to fourteen input reference clock sources from input types T T and T using TTL, CMOS, PECL, LVDS and IN2 IN3 AMI buffer I/O technologies. These interface technologies support +3 ...
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... MHz, • 51.84 MHz, • 77.76 MHz. Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS The frequency selection is programmed via the cnfg_ref_source_frequency register. internal DPLL will normally lock to the selected input at the frequency of the input, eg. 19.44 MHz will lock the DPLL phase comparisons at 19 ...
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... Table 4. Input Reference Source Selection and Priority Table Table 4. Input Reference Source Selection and Priority Table Table 4. Input Reference Source Selection and Priority Table Table 4. Input Reference Source Selection and Priority Table Table 4. Input Reference Source Selection and Priority Table Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS ...
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... Input Wander and Jitter Tolerance Input Wander and Jitter Tolerance Input Wander and Jitter Tolerance Input Wander and Jitter Tolerance The ACS8510 is compliant to the requirements of all relevant standards, principally ITU Recommendation G.825, ANSI DS1.101-1994 and ETS 300 462-5 (1997). All reference clock inputs have a tight frequency tolerance but a generous jitter tolerance ...
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... The ACS8510 performs automatic frequency monitoring with an acceptable input frequency offset range of +/- 16.6 ppm. The ACS8510 DPLL has a programmable frequency limit of +/- 80 ppm. If the range is programmed to be > 16.6 ppm, the frequency monitors should be ...
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... MHz and 77.76 MHz respectively. Output T is differential and can support clocks 155.52 MHz. and can support clocks up to 155.52 MHz. Each output is individually configured to operate at the frequencies shown in Table 8 (configuration must be consistent between ACS8510 devices for protection-switching to be effective - output clocks will be phase-aligned ...
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... O11 MFrSync clocks have a 50:50 mark space ratio. These are driven from the T OUT0 synchronized with their counterparts in a second ACS8510 device (if used), using the technique described later. Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS Jitter and wander frequency (log scale) ...
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... Where the SONSDHB pin is High SONET is default, and when SONSDHB pin is Low SDH is default. Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS Wander and jitter are treated in different ways to reflect their differing impacts on network design. Jitter is always strongly attenuated, whilst wander attenuation can be varied to suit the application and operating state ...
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... Phase Variation Phase Variation Phase Variation Phase Variation There will be a phase shift across the ACS8510 between the selected input reference source and the output clock. This phase shift may vary over time but will be constrained to lie within specified limits. The phase shift is characterised ...
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... Holdover mode). Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS 0.1 Hz 0.3 Hz 0.5 Hz 1.0 Hz 2.0 Hz 4 ANSI Tin1.101-1994, Section 8.2.2, requires that the phase variation be limited so that no more than 255 slips (of 125 µ ...
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... Figure 8. Phase error accumulation of T Figure 8. Phase error accumulation of T Figure 8. Phase error accumulation of T Figure 8. Phase error accumulation Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS output port output port output port output port output port OUT0 OUT0 OUT0 OUT0 OUT0 1 ...
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... During this transition, the Lost_Phase mode is entered. The typical phase disturbance on clock reference source switching will be less than the ACS8510. For clock reference switching caused by the main input failing or being disconnected, then the phase disturbance on the output will still be less than the 120 ns allowed for in the G ...
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... A description of each register is given in the Register Map, and Register Map Description. Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS Interrupt Enable and Clear Interrupt Enable and Clear Interrupt Enable and Clear Interrupt Enable and Clear ...
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... Table 11. Register Map Table 11. Register Map Table 11. Register Map Table 11. Register Map Table 11. Register Map < > < Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS < > < > < > < > < > > < > < > < > < > < > < > < > < > ...
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... Table 11. Register Map (continued). Table 11. Register Map (continued). Table 11. Register Map (continued). Table 11. Register Map (continued Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS < > < > < > < > < > < > < > < > < > < > < > < > < > < > < > < > < > < > < ...
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... ADVANCED COMMUNICATIONS Table 11. Register Map (continued). Table 11. Register Map (continued). Table 11. Register Map (continued). Table 11. Register Map (continued). Table 11. Register Map (continued < Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS > < > < > < > < > < > < > < > < > < > < > ...
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... ADVANCED COMMUNICATIONS Table 11. Register Map (continued). Table 11. Register Map (continued). Table 11. Register Map (continued). Table 11. Register Map (continued). Table 11. Register Map (continued Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS www.semtech.com FINAL ...
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... Register Map Description Register Map Description Register Map Description Register Map Description Register Map Description Table 12. Register Map Description Table 12. Register Map Description Table 12. Register Map Description Table 12. Register Map Description Table 12. Register Map Description Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS ...
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... ADVANCED COMMUNICATIONS Table 12. Register Map Description (continued). Table 12. Register Map Description (continued). Table 12. Register Map Description (continued). Table 12. Register Map Description (continued). Table 12. Register Map Description (continued Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS < > < > www.semtech.com FINAL ...
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... ADVANCED COMMUNICATIONS Table 12. Register Map Description (continued). Table 12. Register Map Description (continued). Table 12. Register Map Description (continued). Table 12. Register Map Description (continued). Table 12. Register Map Description (continued Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS < > < > < > < > < > < ...
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... ADVANCED COMMUNICATIONS Table 12. Register Map Description (continued). Table 12. Register Map Description (continued). Table 12. Register Map Description (continued). Table 12. Register Map Description (continued). Table 12. Register Map Description (continued Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS < > < > < > < > < > < ...
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... ADVANCED COMMUNICATIONS Table 12. Register Map Description (continued). Table 12. Register Map Description (continued). Table 12. Register Map Description (continued). Table 12. Register Map Description (continued). Table 12. Register Map Description (continued Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS < > < > < > < > < > < > < > ...
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... ADVANCED COMMUNICATIONS Table 12. Register Map Description (continued). Table 12. Register Map Description (continued). Table 12. Register Map Description (continued). Table 12. Register Map Description (continued). Table 12. Register Map Description (continued Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS < > < > < > < > www.semtech.com FINAL ...
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... ADVANCED COMMUNICATIONS Table 12. Register Map Description (continued). Table 12. Register Map Description (continued). Table 12. Register Map Description (continued). Table 12. Register Map Description (continued). Table 12. Register Map Description (continued " Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS " www.semtech.com FINAL ...
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... ADVANCED COMMUNICATIONS Table 12. Register Map Description (continued). Table 12. Register Map Description (continued). Table 12. Register Map Description (continued). Table 12. Register Map Description (continued). Table 12. Register Map Description (continued Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS ± ± www.semtech.com FINAL ...
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... ADVANCED COMMUNICATIONS Table 12. Register Map Description (continued). Table 12. Register Map Description (continued). Table 12. Register Map Description (continued). Table 12. Register Map Description (continued). Table 12. Register Map Description (continued Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS < > ° ‘ ‘ ’ < ...
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... A table is maintained which lists all reference sources in the order of priority. This is initially downloaded into the ACS8510 via the microprocessor interface by the Network Manager, and is subsequently modified by the results of the ongoing quality monitoring. In this ...
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... Slave devices is part of the protection mechanism. The availability of each source is determined by a combination of local and remote monitoring of each source. Each input reference source supplied to each ACS8510 device is monitored locally and the results are made available to other devices. Forced Control Selection ...
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... JTAG is not enabled on power-up and the feature has since been enabled. When the TDO output from the ACS8510 is connected to the TDI pin of the next device in the JTAG scan chain, the implementation should be such that a logic change caused by the ...
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... N is the number of the relevent leaky bucket configuration in each case. The default setting are shown in the following: Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS as they occur and the phase locked loop must be temporarily isolated until the clock is once again pure. The clock monitoring process cannot ...
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... Activity Monitoring Activity Monitoring Activity Monitoring Activity Monitoring Activity Monitoring The ACS8510 has a combined inactivity and irregularity monitor. The ACS8510 uses a ‘leaky bucket’ accumulator, which is a digital circuit which mimics the operation of an analog integrator, in which input pulses increase the output amplitude but die away over time ...
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... Pre-Locked mode Pre-Locked mode Pre-Locked mode Pre-Locked mode Pre-Locked mode The ACS8510 will enter the Locked state in a maximum of 100 seconds, as defined by GR- 1244-CORE specification, if the selected reference source is of good quality. device cannot achieve lock within 100 seconds, it reverts to Free-run mode and another reference source is selected ...
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... Holdover mode Holdover mode Holdover mode Holdover mode The Holdover mode is used when the ACS8510 has been in Locked mode for long enough to acquire stable frequency data, but the final selected reference source has become unavailable and a replacement has not yet been qualified for selection ...
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... Master and Slave ACS8510 devices to within one cycle of the 77.76 MHz internal clock. When two ACS8510 devices are to be used in a redundancy-protection scheme within an NE, one will be designated as the Master and the other as the Slave expected that an NE ...
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... The monitoring of the reference sources performed by a Master ACS8510 results in a list of available sources being placed in a sts_valid_sources register. This information is used within the device as one of the masks used to build the device's priority table. The ...
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... This is implemented most simplistically by an external capacitor to GND along with the internal pull-up resistor. The ACS8510 is held in a reset state for 250 ms after the PORB pin has been pulled High. In normal operation PORB should be held High. 45 FINAL www ...
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... Note 1: Both ACS8510 must build a common priority table so that the Slave ACS8510 can select the same input reference source as the Master ACS8510 if the Master fails (when the Master is OK, the Slave locks to the Master's output). Note 2: Slave ACS8510 uses common priority table, built before Master ACS8510 failed - priority table can be modified as ...
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... Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS free-run select ref (state 001) (2) all refs evaluated & & at least one ref valid (main ref invalid or out of lock > ...
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... Table 16. DC Characteristics: TTL Input Port Table 16. DC Characteristics: TTL Input Port Table 16. DC Characteristics: TTL Input Port Table 16. DC Characteristics: TTL Input Port Table 16. DC Characteristics: TTL Input Port Across all operating conditions, unless otherwise stated Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS ...
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... Table 19. DC Characteristics: TTL Output Port Table 19. DC Characteristics: TTL Output Port Table 19. DC Characteristics: TTL Output Port Table 19. DC Characteristics: TTL Output Port Table 19. DC Characteristics: TTL Output Port Across all operating conditions, unless otherwise stated Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS ...
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... Unused differential input ports should be left floating and set in LVDS mode, or the positive and negative inputs tied to VDD and GND respectively. Note 1. Assuming a differential input voltage of at least 100 mV. Note 2. Unused differential input terminated to VDD-1.4 V. Note 3. With 50 load on each pin to VDD-2 V. i.e. 82 Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS ...
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... GND V DD 130R =50 Ω Z 8kHz, 1.544/2.048, O 6.48, 19.44, 38.88, 82R 51.84, 77.76 or =50 Ω 155.52 MHz GND Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS I5POS T06POS 130R I5NEG T06NEG 82R I6POS T07POS 130R I6NEG T07NEG 82R 51 FINAL V DD 130R =50 Ω ...
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... Table 21. DC Characteristics: LVDS Input/Output Port Across all operating conditions, unless otherwise stated ° Note to Table 21 Note to Table 21 Note to Table 21 Note to Table 21 Note to Table 21 Note 1. With 100 load between the differential outputs. Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS FINAL www.semtech.com ...
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... Z 51.84, 77. 155.52 MHz =50 Ω Z 8kHz, 1.544/2.048, O 6.48, 19.44, 38.88, 100R 51.84, 77.76 or =50 Ω 155.52 MHz Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS =50 Ω I5POS T06POS =50 Ω I5NEG T06NEG =50 Ω I6POS T07POS =50 Ω I6NEG T07NEG ...
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... AMI coding with a 50% to 70% duty ratio and the 8 kHz octet phase information by introducing violations in the code rule. The structure of the signals and voltage levels are shown in Figures 14 and 15. Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS ...
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... Figure 15. AMI Input and Output Signal Levels Signal structure of 64 kHz/ 8 kHz central clock interface after suitable transformer. 15.6us 15.6us 7.8us 7.8us + 1. -1.0V -1. Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS 15.6us 15.6us 7.8us 7.8us + 1. -1.0V -1. I_1 TO8POS C1 I_2 TO8NEG ...
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... The AMI differential output TO8POS/TO8NEG should be coupled to a line transformer with a turns ration of 3:1. Components C2 = 470 pF and nF transformer with a turns ratio of 1:1 is used, a 3:1 ratio potential divider R must be used to achieve the required voltage level for the positive and negative pulses. load Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS Turns ratio 1:1 TO8POS R C2 ...
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... Table 24. DC Characteristics: Output Jitter Generation (Test Definition G.812) Across all operating conditions, unless otherwise stated Output jitter generation measured over 60 seconds interval max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905 Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS ...
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... Table 26. DC Characteristics: Output Jitter Generation (Test Definition GR-253-CORE) Across all operating conditions, unless otherwise stated Output jitter generation measured over 60 seconds interval max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905 Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS ...
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... Table 29. DC Characteristics: Output Jitter Generation (Test Definition TR-NWT-000499) Across all operating conditions, unless otherwise stated Output jitter generation measured over 60 seconds interval max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905 & & Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS ...
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... Hz bandwidth, 19.44 MHz direct lock Note 11. 1.2 Hz bandwidth, 8 kHz lock Note 12. 0.6 Hz bandwidth, 19.44 MHz direct lock Note 13. 0.6 Hz bandwidth, 8 kHz lock Note 14 bandwidth, 8 kHz lock, 2.048 MHz input Note 15 bandwidth, 8 kHz lock, 19.44 MHz input Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS ...
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... Table 31. JTAG Timing (for use with Figure 17) Table 31. JTAG Timing (for use with Figure 17) Table 31. JTAG Timing (for use with Figure 17) Table 31. JTAG Timing (for use with Figure 17) Table 31. JTAG Timing (for use with Figure 17 Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS t CYC FINAL ...
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... MHz input 25.92 MHz output 38.88 MHz input 38.88 MHz output 51.84 MHz input 51.84 MHz output 77.76 MHz input 77.76 MHz output Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS Typical Delay Output ± 1 kHz 2 kHz +6 +5 ...
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... Table 32. Read Access Timing in MOTOROLA Mode (for use with Figure 19) Table 32. Read Access Timing in MOTOROLA Mode (for use with Figure 19 Note 1: Timing with RDY. If RDY not used, t Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS t pw1 t su2 t su1 address t d1 data pw2 becomes 178 ns. pw1 www.semtech.com FINAL ...
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... Table 33. Write Access Timing in MOTOROLA Mode (for use with Figure 20) Table 33. Write Access Timing in MOTOROLA Mode (for use with Figure 20 Note 1: Timing with RDY. If RDY not used, t Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS t pw1 t su2 t su1 address t su3 data pw2 becomes 178 ns. pw1 64 FINAL www.semtech.com ...
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... Table 34. Read Access Timing in INTEL Mode (for use with Figure 21) Table 34. Read Access Timing in INTEL Mode (for use with Figure 21 Note 1: Timing with RDY. If RDY not used, t Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS t t su2 su1 ata becomes 180 ns. pw1 www.semtech.com FINAL ...
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... Table 35. Write Access Timing in INTEL Mode (for use with Figure 22 Note 1: Timing with RDY. If RDY not used, t Note 2: Timing greater than 170 ns, otherwise 5 ns after CSB rising edge. h2 Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS t t su2 pw1 t su1 address t su3 data pw2 becomes 180 ns. pw1 www.semtech.com FINAL ...
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... Table 36. Read Access Timing in MULTIPLEXED Mode (for use with Figure 23) Table 36. Read Access Timing in MULTIPLEXED Mode (for use with Figure 23) Table 36. Read Access Timing in MULTIPLEXED Mode (for use with Figure 23 Note 1: Timing with RDY. If RDY not used, t Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS becomes 180 ns. pw1 www.semtech.com FINAL ...
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... Table 37. Write Access Timing in MULTIPLEXED Mode (for use with Figure 24) Table 37. Write Access Timing in MULTIPLEXED Mode (for use with Figure 24) Table 37. Write Access Timing in MULTIPLEXED Mode (for use with Figure 24 Note 1: Timing with RDY. If RDY not used, t Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS becomes 180 ns. pw1 www.semtech.com FINAL ...
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... R/W SDO Output not driven, pulled low by internal resistor CLKE = 1; SDO data is clocked out on the falling edge of SCLK CSB SCLK SDI R/W Output not driven, pulled low by internal resistor SDO Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS t pw2 t pw1 FINAL t ...
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... Table 39. Write Access Timing in SERIAL Mode (for use with Figure 26) Table 39. Write Access Timing in SERIAL Mode (for use with Figure 26) Table 39. Write Access Timing in SERIAL Mode (for use with Figure 26) Table 39. Write Access Timing in SERIAL Mode (for use with Figure 26 Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS ...
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... EPROM Mode EPROM Mode In EPROM mode, the ACS8510 takes control of the bus as Master, and reads the device set-up from an AMD AM27C64 type EPROM at lowest speed (250ns), after device start-up (system reset). The EPROM access state machine in the up interface sequences the accesses. ...
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... Exact shape of corners can vary defined as the distance from the seating plane to the lowest point of the package body. 7 These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 8 Shows plating. Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS ...
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... Figure 29. Typical 100 Pin LQFP Footprint Figure 29. Typical 100 Pin LQFP Footprint Pitch 0.5 mm Notes (1) Solderable to this limit. Square package - dimensions apply in both X and Y directions. Typical example. The user is reponsible for ensuring compatibility with PCB manufacturing process, etc. Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS ...
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... ADVANCED COMMUNICATIONS Application Information Application Information Application Information Application Information Application Information Figure 30. Simplified Application Schematic Figure 30. Simplified Application Schematic Figure 30. Simplified Application Schematic Figure 30. Simplified Application Schematic Figure 30. Simplified Application Schematic Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS 74 FINAL www.semtech.com ...
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... Table 42. Changes from Revision 1.06 to 2.00 September 2003 Table 42. Changes from Revision 1.06 to 2.00 September 2003 Table 42. Changes from Revision 1.06 to 2.00 September 2003 Item Section Page Non-Revertive 1 36-37 Mode Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS Description Updated description of Non-Revertive Mode Operation 75 FINAL www.semtech.com ...
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... No. 46, Lane 11, Kuang Fu North Road, Taipei, Taiwan, R.O.C. Tel: +886 2 2748 3380, Fax: +886 2 2748 3390 EUROPE: Units 2 & 3 Park Court, Premier Way, Abbey Park Industrial Estate, Romsey, Hampshire, SO51 9DN, UK Tel: +44 1794 527 600, Fax: +44 1794 527 601 Revision 2.00/September 2003 Semtech Corp. ACS8510 Rev2.1 SETS ...