ACS8510 Semtech, ACS8510 Datasheet - Page 11

• Manufacturer Part Number: ACS8510
• Manufacturer: Semtech

Specifications of ACS8510

• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6/5.5V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Package Type: LQFP
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / Rohs Status: Not Compliant

Input Reference Clock Ports
Input Reference Clock Ports
Input Reference Clock Ports
Input Reference Clock Ports
Input Reference Clock Ports
Table 4 gives details of the input reference
ports, showing the input technologies and the
range of frequencies supported on each port;
the default spot frequencies and default
priorities assigned to each port on power-up or
by reset are also shown. Note that SDH and
SONET networks use different default
frequencies; the network type is pin-selectable
(using the SONSDHB pin). Specific frequencies
and priorities are set by configuration.
Although each input port is shown as belonging
to one of the types, T
fully interchangeable as long as the selected
speed is within the maximum operating speed
of the input port technology.
SDH and SONET networks use different default
frequencies; the network type is selectable
using the config_mode register 34 Hex, bit 2.
For SONET, config_mode register 34 Hex, bit 2
= 1, for SDH config_mode register 34 Hex, bit
2 = 0. On power-up or by reset, the default will
be set by the state of the SONSDHB pin (pin
100). Specific frequencies and priorities are set
by configuration.
TTL ports (compatible also with CMOS signals)
support clock speeds up to 100 MHz, with the
highest spot frequency being 77.76 MHz. The
actual spot frequencies supported are:
• 2 kHz
• 4 kHz
• 8 kHz (and N x 8 kHz)
• 1.544 MHz (SONET)/2.048 MHz (SDH)
• 6.48 MHz,
• 19.44 MHz,
• 25.92 MHz,
• 38.88 MHz,
• 51.84 MHz,
• 77.76 MHz.
Revision 2.00/September 2003
ADVANCED COMMUNICATIONS
IN1
, T
Semtech Corp.
IN2
or T
IN3
, they are
11
The frequency selection is programmed via the
cnfg_ref_source_frequency register.
internal DPLL will normally lock to the selected
input at the frequency of the input, eg. 19.44
MHz will lock the DPLL phase comparisons at
19.44 MHz. It is, however, possible to utilise
an internal pre-divider to the DPLL to divide the
input frequency before it is used for phase
comparisons in the DPLL. This pre-divider can
be used in one of 2 ways:
1. Any of the supported spot frequencies can be divided to
8 kHz by setting the ‘lock8K’ bit (bit 6) in the appropriate
cnfg_ref_source_frequency register location. For good jitter
tolerance for all frequencies and for operation at
19.44 MHz and above, use lock8K. It is possible to choose
which edge of the 8kHz input to lock to, by setting the
appropriate bit of the cnfg_control1 register.
2. Any multiple of 8 kHz between 1544 kHz to 100 MHz
can be supported by using the ‘DivN’ feature (bit 7 of the
cnfg_ref_source_frequency register). Any reference input
can be set to use DivN independently of the frequencies
and configurations of the other inputs.
Any reference input with the DivN bit set in the
cnfg_ref_source_frequency register will employ
the internal pre-divider prior to the DPLL locking.
The cnfg_freq_divn register contains the divider
ratio N where the reference input will get divided
by
cnfg_ref_source_frequency register must be set
to the closest supported spot frequency to the
input frequency, but must be lower than the
input frequency. When using the DivN feature
the post-divider frequency must be 8 kHz, which
is indicated by setting the ‘lock8k’ bit high (bit
6 in cnfg_ref_source_frequency register). Any
input set to DivN must have the frequency
monitors disabled (If the frequency monitors
are disabled, they are disabled for all inputs
regardless of the input configurations, in this
case only activity monitoring will take place).
Whilst any number of inputs can be set to use
the DivN feature, only one N can be
programmed, hence all inputs using the DivN
feature must require the same division to get
to 8 kHz.
ACS8510 Rev2.1 SETS
(N+1)
where
0<N<2
14
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-1.
FINAL
The
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