S29GL256M10TAIR10 Spansion Inc., S29GL256M10TAIR10 Datasheet - Page 68

• Manufacturer Part Number: S29GL256M10TAIR10
• Manufacturer: Spansion Inc.

Specifications of S29GL256M10TAIR10

• Cell Type: NOR
• Density: 256Mb
• Access Time (max): 100ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 25/24Bit
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 3/11.5 to 12.5V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 32M/16M
• Supply Current: 60mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

Chip Erase Command Sequence
Sector Erase Command Sequence
66
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing
two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then
followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The
device does not require the system to preprogram prior to erase. The Embedded Erase algorithm
automatically preprograms and verifies the entire memory for an all zero data pattern prior to
electrical erase. The system is not required to provide any controls or timings during these oper-
ations.
command sequence.
When the Embedded Erase algorithm is complete, the device returns to the read mode and ad-
dresses are no longer latched. The system can determine the status of the erase operation by
using DQ7, DQ6, or DQ2. See
Any commands written during the chip erase operation are ignored. However, note that a hard-
ware reset immediately terminates the erase operation. If that occurs, the chip erase command
sequence should be reinitiated once the device returns to reading array data, to ensure data
integrity.
Figure 6
mance
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writ-
ing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written,
and are then followed by the address of the sector to be erased, and the sector erase command.
Table 34
sequence.
in
Table 34
illustrates the algorithm for the erase operation. See
and
AC Characteristics
Table 35
No
Figure 5. Program Suspend/Program Resume
and
Sequence in Progress
Program Operation
Write address/data
Write address/data
Table 35
Program Suspend
or Write-to-Buffer
Device reverts to
operation prior to
Read data as
shows the address and data requirements for the sector erase command
XXXh/B0h
Wait 15 μs
XXXh/30h
reading?
required
S29GL-M MirrorBit
Done
for parameters, and
Yes
show the address and data requirements for the chip erase
Write Operation Status
D a t a
Write Program Suspend
Command Sequence
Command is also valid for
Erase-suspended-program
operations
Autoselect and SecSi Sector
read operations are also allowed
Data cannot be read from erase- or
program-suspended sectors
Write Program Resume
Command Sequence
TM
Flash Family
S h e e t
Figure 18
for information on these status bits.
for timing diagrams.
Erase and Programming Perfor-
S29GL-M_00_B8 February 7, 2007