HI-8588PST Holt Integrated Circuits, HI-8588PST Datasheet - Page 2

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HI-8588PST

Manufacturer Part Number
HI-8588PST
Description
Manufacturer
Holt Integrated Circuits
Datasheet

Specifications of HI-8588PST

Operating Temperature Classification
Military
Operating Temperature (max)
125C
Package Type
SOIC N
Rad Hardened
No
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HI-8588PST
Manufacturer:
TOUCHSTON
Quantity:
1 001
Part Number:
HI-8588PST-10
Manufacturer:
HOLT
Quantity:
101
FUNCTIONAL DESCRIPTION
RECEIVER
Figure 1 shows the general architecture of the ARINC 429
receiver. The receiver operates off the VCC supply only.
The inputs RINA and RINB each have series resistors, typi-
cally 35K ohms. They connect to level translators whose
resistance to Ground is typically 10K ohms. Therefore, any
series resistance added to the inputs will affect the voltage
translation.
After level translation, the inputs are buffered and become
inputs to a differential amplifier. The amplitude of the differ-
ential signal is compared to levels derived from a divider be-
tween VCC and Ground. The nominal settings correspond
to a One/Zero amplitude of 6.0V and a Null amplitude of
3.3V.
APPLICATION INFORMATION
Figure 2 shows a possible application
of the HI-8588 interfacing an ARINC re-
ceive channel to the HI-6010 which in
turn interfaces to an 8-bit bus.
RINA
RINB
TRANSLATION
PROTECTION
ESD
AND
FIGURE 1 - RECEIVER BLOCK DIAGRAM
FIGURE 2 - APPLICATION DIAGRAM
HOLT INTEGRATED CIRCUITS
ARINC
Channel
ARINC
Channel
HARDWIRE
DRIVE FROM LOGIC
OR
HI-8588
ZERO
NULL
NULL
ONE
2
{
The status of the ARINC receiver input is latched. A
Null input resets the latches and a One or Zero input
sets the latches.
The logic at the output is controlled by the test signal
which is generated by the logical OR of the TESTA and
TESTB pins. If TESTA and TESTB are both One, then
the receiver is powered down and the output pins float.
The powerdown does not disconnect the internal resis-
tors at the ARINC input.
S
LATCH
R
S
LATCH
R
4
3
6
7
2
8
Q
Q
TXAOUT
TXBOUT
TESTA
TESTB
RINA
RINB
5
4
GND
HI-8586
HI-8588
SLP1.5
1
5V
VCC
TEST
TEST
TESTA
TEST
TEST
TESTB
-15V
5
1
15V
V-
V+
ROUTA
ROUTB
TX1IN
TX0IN
8
6
7
3
2
RXD1
RXD0
TXD1
TXD0
HI-6010
TESTA ' TESTB
TESTA ' TESTB
8 BIT BUS
ROUTA
ROUTB

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