B69000 Asiliant Technologies, B69000 Datasheet - Page 187

• Manufacturer Part Number: B69000
• Manufacturer: Asiliant Technologies

Specifications of B69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

14-20
XR70
read-only at I/O address 3D7h with index at I/O address 3D6h set to 70h
The bits of this register indicate the state of each of these pins at the time the graphics controller is reset.
During a reset, the graphics controller does not drive these pins, thereby allowing them to either be pulled
high by relatively weak internal resistors, or to be pulled low by external resistors (4.7K recommended).
Instead, during reset, the graphics controller latches the state of these pins, and the latched values are used
by the graphics controller to provide a limited degree of hardware-based configuration of some features.
Some of these latched values directly affect the hardware, while others are simply reflected in this register
so as to be read by configuration software, usually the BIOS.
7
Note:
6
5
4
Note:
&+,36
CFG7
(x)
7
Pin CFG7
0: Enables clock test mode.
1: Disables clock test mode.
Clock test mode allows the internal clock synthesizers to be tested, by placing the output of the
MCLK synthesizer on the ROMOE# pin (the pin used to drive the chip select pin of the BIOS ROM)
and the output of the VCLK synthesizer on the PCLK pin (the clock pin used for the video data port).
Pin CFG6
0: The ACTI and ENABKL outputs are forced to be tri-stated.
1: The ACTI and ENABKL outputs are permitted to function normally.
Pin CFG5
Reserved.
No interpretation has yet been assigned to the state of this bit, and the hardware does not interpret
the state of the corresponding pin during reset.
Pin CFG4
0: The REFCLK and TCLK pins are used as inputs to receive MCLK an DCLK, respectively, from
an external source.
1: MCLK and DCLK are provided by the internal clock generators.
The default selection of sources for MCLK and DCLK may be individually changed by changing the
settings of bits 2 and 1 of the Memory Clock Divisor Select Register (XRCF). Both of those two bits
also use the state of pin AA4 at reset to determine their default values.
69000 Databook
Configuration Pins 0 Register
CFG6
(x)
6
CFG5
(x)
5
Subject to Change Without Notice
Extension Registers
CFG4
(x)
4
CFG3
(x)
3
CFG2
(x)
2
CFG1
(x)
Revision 1.3 8/31/98
1
Reserved
(1)
0