SC2614MLTR Semtech, SC2614MLTR Datasheet - Page 9

• Manufacturer Part Number: SC2614MLTR
• Manufacturer: Semtech

Specifications of SC2614MLTR

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 18
• Mounting: Surface Mount
• Package Type: MLP
• Case Length: 6mm
• Screening Level: Commercial
• Lead Free Status / Rohs Status: Not Compliant

Description
The Semtech SC2614 DDR power supply controller is
the latest and most complete, three in one, switching
and linear regulator, providing the necessary functions
to comply with S3 and S5 sleep state signals generated
by the Desktop Computer Motherboards. The SC2614
uses the BF_CUT
externally on Intel P4 Motherboard glue chip to comply
with the power sequencing requirements.
Logically, the BF_CUT signal can be represented as:
BF_CUT=S0 .NAND.P_OK
Where S0 is the state of the operation, S0=high for S0
and Low for S3. P_OK is a signal generated by the
Silverbox supply, indicating that all rails are within
specification .
The BF_CUT signal is inverted to drive a Back_Feed_Cut
MOSFET. The Back_Feed_Cut MOSFET prevents current
flow from the VDDq supply back to the 5V supply during
S3 state (when BF_CUT is high). VDDQ supply and the
VTT termination voltages are supplied to the Memory bus
during S0 (normal operation).
During S0, VDDQ is supplied via the Switching regulator,
sourcing high output currents to the VDD bus which in
turn sources the termination supply current. The SC2614
is capable of driving a 4000pf capacitor in 25ns (typical,
top gate). This drive capability allows 15-20A DC load on
the VDDQ supply.
The VTT termination voltage is an internal sink/source
linear regulator, which during S0 state receives its power
from the VDDQ bus. It is capable of sourcing and sinking
2 Amps (max). The current limit on this pin is set to 3
Amps (typical). The current handling capacity of this pin
depends upon the amount of heat the PC board can sink
from the SC2614 thermal pad. (See mounting
instructions). The PC board layout must take into
consideration the high current paths, and ground returns
for both the VDDQ and VTT supply pins. VTT, LGND,
VDDQ, 5VCC and PGND traces must also be routed using
wide traces to minimize power loss and heat in these
traces, based on the current handling requirements.
POWER MANAGEMENT
Applications Information
© 2004 Semtech Corp.
BF_CUT
BF_CUT
BF_CUT
BF_CUT input signal which is generated
9
S3 and S5 States
During S3 and S5 sleep states, The BF_CUT signal is
pulled high (see the timing diagram). The operation of
the VDDQ and VTT supplies is governed by the internal
sequencing logic in strict adherence with intel
specifications with regards to the BF_CUT sgnal. The
timing diagram demonstrates the state of the controller,
and each of the VDDQ and VTT supplies during S3 and
S5 transitions. When S3 is low, the VDDQ supplies the
“Suspend To RAM” current of 650 mA (max) to maintain
the information in memory while in standby mode. The
VTT termination voltage is not needed during this state,
and is thus tri-stated. Once BF_CUT goes low, the VDDQ
switcher recovers and takes control of the VDDQ supply
voltage.
The SS/EN pin must be pulled low and high again to restart
the SC2614. This can be achieved by cycling the input
supplies, 5V or 12V.
Initial Conditions
With the S5 and S3 go high (BF_CUT goes low) for the
first time, the VDDQ is supplied by the Switcher, thus
removing the burden of charging the output capacitors
via the linear VDDQ regulator.
Back-feeding the Input Supply
When in S3 state, VDDQ is supplied by the linear regulator
and current can flow back from the VDDQ supply through
the body diode of the Top switching MOSFET to the 5V
supply in the Silver Box. Since the 5VCC is off during this
state, this back flow of current in effect shorts out the
VDDQ supply and is not desirable.
The blocking MOSFET is driven from the inverted BF_CUT
signal, as shown in figure 2 (Evaluation Board
Schematic). When the gate voltage for this series MOSFET
is low, the current can not flow from the VDDQ supply
back into the input power source.
Current Limit
Current limit is implemented by sensing the VDDQ voltage
If it falls to 60% off its nominal voltage, as sensed by the
FB pin, the TG and BG pins are latched off and the
switcher and the linear controllers are shutdown. To
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