S29AL016D90TFI02 Spansion Inc., S29AL016D90TFI02 Datasheet - Page 16

• Manufacturer Part Number: S29AL016D90TFI02
• Manufacturer: Spansion Inc.

Specifications of S29AL016D90TFI02

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 90ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 21/20Bit
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 2M/1M
• Supply Current: 35mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Compliant

7.5
7.6
7.7
16
Standby Mode
Automatic Sleep Mode
RESET#: Hardware Reset Pin
When the system is not reading or writing to the device, it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state,
independent of the OE# input.
The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V
(Note that this is a more restricted voltage range than V
V
requires standard access time (t
before it is ready to read data.
If the device is deselected during erasure or programming, the device draws active current until the operation
is completed.
I
on page
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables
this mode when addresses remain stable for t
CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are
changed. While in sleep mode, output data is latched and always available to the system. I
Characteristics on page 37
The RESET# pin provides a hardware method of resetting the device to reading array data. When the system
drives the RESET# pin to V
progress, tristates all data output pins, and ignores all read/write attempts for the duration of the RESET#
pulse. The device also resets the internal state machine to reading array data. The operation that was
interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure
data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held at V
draws CMOS standby current (I
will be greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firmware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a 0 (busy) until the
internal reset operation is complete, which requires a time of t
system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not executing (RY/BY# pin is 1), the reset operation is
completed within a time of t
RESET# pin returns to V
Refer to the tables in
for the timing diagram.
CC3
CC
± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device
and I
37.
CC4
represents the standby current specification shown in the table in
AC Characteristics on page 40
IH
.
IL
READY
represents the automatic sleep mode current specification.
for at least a period of t
CC4
CE
(not during Embedded Algorithms). The system can read data t
) for read access when the device is in either of these standby modes,
). If RESET# is held at V
S29AL016D
D a t a
ACC
+ 30 ns. The automatic sleep mode is independent of the
RP
for RESET# parameters and to
, the device immediately terminates any operation in
S h e e t
IH
.) If CE# and RESET# are held at V
IL
READY
but not within V
(during Embedded Algorithms). The
S29AL016D_00_A8 February 27, 2009
SS
DC Characteristics
±0.3 V, the standby current
Figure 17.2 on page 41
SS
±0.3 V, the device
CC4
IH
, but not within
in the
CC
RH
± 0.3 V.
after the
DC