DSPB56364FU100 Freescale Semiconductor, DSPB56364FU100 Datasheet

Page 1

... DSP56364 offers 100 million instructions per second (MIPS) using an internal 100 MHz clock at 3.3 V. Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2006, 2007. All rights reserved. Document Number: DSP56364 Rev. 4.1, 10/2007 Contents 1 Overview ...

Page 2

... DSP56364 Technical Data, Rev. 4.1 Signal State Voltage* Asserted Deasserted Asserted Deasserted MEMORY RAM 1. MEMORY EXPANSION AREA ADDRESS EXTERNAL 18 ADDRESS BUS SWITCH CONTROL DRAM & SRAM 6 BUS INTERFACE DATA EXTERNAL 8 DATA BUS SWITCH POWER MGMT 4 JTAG OnCE™ 24 BITS BUS Freescale Semiconductor ...

Page 3

... Unused pins of ESAI may be used as GPIO lines. • Serial Host Interface (SHI): SPI and I 24-bit words. • Four dedicated GPIO lines. Freescale Semiconductor 7). Reduces clock noise Sony, AC97, network and other programmable protocols protocols, 10-word receive FIFO, support for 8, 16 and DSP56364 Technical Data, Rev ...

Page 4

... Detailed description of the 56000-family architecture and the 24-bit core processor and instruction set Detailed description of memory, peripherals, and interfaces Brief description of the chip Electrical and timing specifications; pin and package descriptions DSP56364 Technical Data, Rev. 4.1 Order Number DSP56300FM DSP56364UM DSP56364P DSP56364 Freescale Semiconductor ...

Page 5

... Port A is the external memory interface port, including the external address bus, data bus, and control signals. 2 Port B signals are the GPIO signals. 3 Port C signals are the ESAI port signals multiplexed with the GPIO signals. Freescale Semiconductor 2-1. 1 Port A 2 Port B ...

Page 6

... DSP56364 Technical Data, Rev. 4.1 JTAG PORT TDI TCK TDO TMS PB0-PB3 SCKT [PC3] FST [PC4] HCKT [PC5] SCKR [PC0] FSR [PC1] HCKR [PC2] SDO0 [PC11] SDO1 [PC10] SDO2/SDI3 [PC9] SDO3/SDI2 [PC8] SDO4/SDI1 [PC7] SDO5/SDI0 [PC6] VCCSS (3) GNDS (3) MOSI/HA0 SS /HA2 MISO/SDA SCK/SCL HREQ Freescale Semiconductor ...

Page 7

... Data Bus Ground—GND D must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There is one GND Freescale Semiconductor Table 2-2 Power Inputs Description is V dedicated for PLL use. The voltage should be well-regulated and the input should isolated power for the internal processing logic ...

Page 8

... Otherwise, the signals are kept to their previous values by internal weak keepers. To minimize power dissipation, A0–A17 do not change state when external memory spaces are not being accessed. DSP56364 Technical Data, Rev. 4.1 CCP , GND, or left floating. CC Signal Description Freescale Semiconductor . ...

Page 9

... Tri-stated TA Input Ignored Input Transfer Acknowledge—If there is no external bus activity, the Freescale Semiconductor Table 2-6 External Data Bus Signals Signal Description Data Bus—D0–D7 are active-high, bidirectional input/outputs that provide the bidirectional data bus for external program and data memory accesses. D0–D7 are tri-stated during hardware reset and when the DSP is in the stop or wait low-power standby mode ...

Page 10

... A stable EXTAL signal must be supplied before deassertion of This input tolerant. DSP56364 Technical Data, Rev. 4.1 IRQA is an active-low RESET IRQB is an active-low RESET signal is IRQD is an active-low RESET signal is signal is deasserted, the initial chip RESET . Freescale Semiconductor signal ...

Page 11

... MOSI Input or Tri-stated output Freescale Semiconductor Table 2-9 Serial Host Interface Signals Signal Description SPI Serial Clock—The SCK signal is an output when the SPI is configured as a master and a Schmitt-trigger input when the SPI is configured as a slave. When the SPI is configured as a master, the SCK signal is derived from the internal SHI clock generator ...

Page 12

... HREQ to proceed to the next transfer. This signal is tri-stated during hardware, software, personal reset, or when the HREQ1–HREQ0 bits in the HCSR are cleared. There is no need for external pull-up in this state. This input tolerant. DSP56364 Technical Data, Rev. 4 master mode master mode. Freescale Semiconductor ...

Page 13

... FST Input or output GPIO disconnected Freescale Semiconductor Signal Description High Frequency Clock for Receiver—When programmed as an input, this signal provides a high frequency clock source for the ESAI receiver as an alternate to the DSP core clock. When programmed as an output, this signal can serve as a high-frequency sample clock (e ...

Page 14

... Port C 6—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input tolerant. Serial Data Output 4—When programmed as a transmitter, SDO4 is used to transmit data from the TX4 serial transmit shift register. DSP56364 Technical Data, Rev. 4.1 Freescale Semiconductor ...

Page 15

... PC11 Input, output, or GPIO disconnected disconnected Freescale Semiconductor Signal Description Serial Data Input 1—When programmed as a receiver, SDI1 is used to receive serial data into the RX1 serial receive shift register. Port C 7—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. ...

Page 16

... Reset GPIO0–3—The General Purpose I/O pins are used for control and handshake functions between the DSP and external circuitry. Each Port B GPIO pin may be individually programmed as an input, output or disconnected DSP56364 Technical Data, Rev. 4.1 Signal Description Freescale Semiconductor ...

Page 17

... Therefore, a “maximum” value for a specification will never occur in the same device that has a “minimum” value for another specification; adding a maximum to a minimum represents a condition that can never exist. Freescale Semiconductor CAUTION ). The suggested value for a pull-up or pull-down CC NOTE DSP56364 Technical Data, Rev ...

Page 18

... Table 3-2 Thermal Characteristics Symbol 1 R θJA R θJC Ψ DSP56364 Technical Data, Rev. 4 Value − 0.3 to +4.0 GND -0 0.3 CC − GND 0 3. -40 to +105 − +125 TQFP Value or θ 49. θ 9.26 JC 2.0 JT Freescale Semiconductor Unit ° C ° C Unit ° C/W ° C/W ° C/W ...

Page 19

... Refers to MODA/IRQA, MODB/IRQB, and MODD/IRQD pins 3 Driving EXTAL to the low V or the high V IHX power consumption, the minimum V 0.1 × Periodically sampled and not 100% tested Freescale Semiconductor Table 3-3 DC Electrical Characteristics Symbol Min 2.0 IHP V 1.5 IHP 0.8 × ...

Page 20

... PDF × DF/MF DSP56364 Technical Data, Rev. 4 105°C. maximum IL and V reference levels set Expression Typ Max (Ef × MF)/ — (PDF × DF) Ef/2 — ET — C 0.51 × ET — C PDF × DF/MF 0.53 × ET — C PDF × DF/MF Freescale Semiconductor J × × ...

Page 21

... External Clock Operation The DSP56364 system clock is an externally supplied square wave voltage source connected to EXTAL (See Figure 3-1). EXTAL ETH V ILC Note: The midpoint is 0.5 (V Freescale Semiconductor Table 3-4 Internal Clocks (continued) Symbol Min T L — 0.49 × ET × C PDF × DF/MF 0.47 × ...

Page 22

... DSP56364 Technical Data, Rev. 4.1 Symbol Min Max Ef 0 100.0 ∞ 157.0 μs 4.25 ns ∞ 157.0 μs 4.25 ns ∞ ET 10. 273.1 μs 10.00 ns Max Unit 200 MHz pF (MF × 780) − 140 MF × 1470 ). The recommended value in pF for CCP Freescale Semiconductor ...

Page 23

... Delay from address output valid caused by first interrupt instruction execute to interrupt request deassertion for level 6, 7 sensitive fast interrupts RD 20 Delay from assertion to interrupt request deassertion for level sensitive fast interrupts Freescale Semiconductor Reset, Stop, Mode Select, and Interrupt Timing 3 deassertion to first 5 3.25 × T 20.25 T NMI , assertion to external 4.25 × ...

Page 24

... C 5.9 — × PDF + 1.3 13 × PDF + 232.5 12 77.5 87.5 C × PDF + 13.6 — × PDF + 12.3 — 5.5 × T 55.0 — C 12T — 120 — 80 — 80.0 C 12T — 120 — 60 — 70 — 30.0 C Freescale Semiconductor Unit ...

Page 25

... The maximum value for ET is 4096 (maximum MF) divided by the desired internal frequency (i.e., for 100 MHz it is 4096/100 C MHz = 40 μs). During the stabilization period well PLL does not lose lock. Freescale Semiconductor Reset, Stop, Mode Select, and Interrupt Timing Expression 4.25 × T NMI , ...

Page 26

... Purpose I/O IRQA, IRQB, IRQD, NMI 3-10 9 Reset Value Figure 3-2 Reset Timing F nstruction irst Interrupt I Execution/Fetch First Interrupt Instruction Execution 18 b) General Purpose I/O Figure 3-3 External Fast Interrupt Timing DSP56364 Technical Data, Rev. 4 First Fetch AA0460 AA0462 Freescale Semiconductor ...

Page 27

... IRQD, NMI IRQA, IRQB, IRQD, NMI Figure 3-4 External Interrupt Timing (Negative Edge-Triggered) RESET MODA, MODB,MODD, PINIT IRQA A0–A17 Figure 3-6 Recovery from Stop State Using IRQA Freescale Semiconductor Figure 3-5 Operating Mode Select Timing 24 25 DSP56364 Technical Data, Rev. 4.1 ...

Page 28

... RC WC DSP56364 Technical Data, Rev. 4.1 First IRQA Interrupt Instruction Fetch AA0467 AA1104 1 2 Expression Min Max ( × T − 4.0 16.0 — ≤ WS ≤ × T − 4.0 56.0 — ≤ WS ≤ × T − 4.0 106.0 — C [WS ≥ 8] Freescale Semiconductor Unit ...

Page 29

... WR deassertion to address not valid 104 Address and AA valid to input data valid 105 RD assertion to input data valid 106 RD deassertion to data not valid (data hold time) 107 Address valid to WR deassertion Freescale Semiconductor Symbol Expression 0.25 × 0.75 × ≤ WS ≤ 3] 1.25 × T 1.5 × ...

Page 30

... C − 4.0 1.0 — C − 2.0 6.0 — C − 4.0 21.0 — C − 4.0 31.0 — C − 4.0 1.0 — C −4.0 8.5 — C − 2.0 0.5 — C − 2.0 10.5 — C − 2.0 20.5 — C Freescale Semiconductor Unit ...

Page 31

... WS is the number of wait states specified in the BCR. 3 Timings 100, 107 are guaranteed by design, not tested the case of TA negation: timing 118 is relative to the deassertion edge were TA to remain active. A0–A17 AA0–AA1 D0–D7 Freescale Semiconductor Symbol Expression 4 0.25 × T 100 113 116 115 105 104 ...

Page 32

... Figure 3-10 SRAM Write Access Figure 3-11 and Figure 3-14 should be used for primary selection only. DSP56364 Technical Data, Rev. 4.1 103 118 111 109 Data Out AA0469 Freescale Semiconductor ...

Page 33

... Page mode cycle time for mixed (read and write) accesses 132 CAS assertion to data valid (read) 133 Column address valid to data valid (read) Freescale Semiconductor Note: This figure should be use for primary selection. For exact and detailed timings see the following tables. Chip Frequency (MHz) 120 66 ...

Page 34

... Freescale Semiconductor ...

Page 35

... Reduced DSP clock speed allows use of Page Mode DRAM with one Wait state (See 5 BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of-page access deassertion will always occur after CAS deassertion; therefore, the restricted timing is t Freescale Semiconductor Symbol Expression 1.5 × T − 4.0 t ...

Page 36

... Freescale Semiconductor ...

Page 37

... All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., t read-after-read or write-after-write sequences). 6 BRW[1:0] (DRAM Control Register bits) defines the number of wait states that should be inserted in each DRAM out-of-page access deassertion will always occur after CAS deassertion; therefore, the restricted timing is t Freescale Semiconductor Symbol Expression 2.75 × RWL C 2.5 × ...

Page 38

... C 3.5 × T − 4.5 30.5 — 3.75 × T − 4.3 33.2 — 3.25 × T − 4.3 28.2 — 0.5 × T − 4.0 1.0 — 2.5 × T − 4.0 21.0 — 1.25 × T − 4.3 8.2 — Freescale Semiconductor ...

Page 39

... Last CAS assertion to RAS deassertion 136 Previous CAS deassertion to RAS deassertion 137 CAS assertion pulse width 138 Last CAS deassertion to RAS assertion • BRW[1: • BRW[1: • BRW[1: • BRW[1: 139 CAS deassertion pulse width Freescale Semiconductor Symbol t ROH Symbol CAC ...

Page 40

... C 1.25 × T − 4.3 8.2 — C 4.5 × T − 4.0 41.0 — C 3.25 × T − 7.0 — 25.5 C 0.0 — 0.75 × T − 0.3 7.2 — C 0.25 × T — 2 equals 3 × and not t . OFF GZ Freescale Semiconductor for C ...

Page 41

... RAS CAS Row A0–A17 Add WR RD D0–D7 Figure 3-12 DRAM Page Mode Write Accesses Freescale Semiconductor 131 137 139 140 141 Column Column Address Address 151 144 145 146 155 150 149 Data Out Data Out DSP56364 Technical Data, Rev. 4.1 ...

Page 42

... Figure 3-13 DRAM Page Mode Read Accesses 3-26 131 137 139 140 141 Column Column Address Address 143 133 153 Data In Data In DSP56364 Technical Data, Rev. 4.1 136 135 138 142 Last Column Address 132 152 134 154 Data In AA0474 Freescale Semiconductor ...

Page 43

... Column address valid to data valid (read) 161 CAS deassertion to data not valid (read hold time) 162 RAS deassertion to RAS assertion 163 RAS assertion pulse width 164 CAS assertion to RAS deassertion Freescale Semiconductor 66 80 100 120 11 Wait States 15 Wait States Symbol Expression 5 × ...

Page 44

... Freescale Semiconductor Unit ...

Page 45

... CAS assertion to data valid (read) 160 Column address valid to data valid (read) 161 CAS deassertion to data not valid (read hold time) 162 RAS deassertion to RAS assertion 163 RAS assertion pulse width Freescale Semiconductor Symbol Expression 3 × T − 4.3 t WCS C 0.5 × T − 4.0 t ...

Page 46

... Freescale Semiconductor Unit ...

Page 47

... CAS assertion to data valid (read) 160 Column address valid to data valid (read) 161 CAS deassertion to data not valid (read hold time) 162 RAS deassertion to RAS assertion 163 RAS assertion pulse width Freescale Semiconductor 4 Symbol Expression 3.25 × T − 4 5.75 × T − ...

Page 48

... C − 4.5 110.5 — C − 4.3 113.2 — C − 4.3 103.2 — C − 4.0 53.5 — C − 4.0 48.5 — C − 4.0 73.5 — C − 4.3 60.7 — C − 4.0 11.0 — C − 4.0 23.5 — C Freescale Semiconductor Unit ...

Page 49

... CAS assertion pulse width 167 RAS assertion to CAS assertion 168 RAS assertion to column address valid 169 CAS deassertion to RAS assertion 170 CAS deassertion pulse width 171 Row address valid to RAS assertion 172 RAS assertion to row address not valid Freescale Semiconductor 3 Symbol t ROH Symbol t ...

Page 50

... T − 4.0 11.0 — C 4.75 × T − 4.0 43.5 — C 15.5 × T − 4.0 151.0 — × T − 5.7 — 134.3 C 0.0 — 0.75 × T − 0.3 7.2 — C 0.25 × T — 2.5 C and not t . OFF GZ Freescale Semiconductor Unit ...

Page 51

... RAS 169 CAS A0–A17 WR RD D0–D7 Figure 3-15 DRAM Out-of-Page Read Access Freescale Semiconductor 157 163 165 167 164 168 170 166 171 173 175 Row Address Column Address 172 176 177 191 160 159 158 192 DSP56364 Technical Data, Rev. 4.1 ...

Page 52

... Row Address Column Address 181 175 188 180 182 184 183 187 186 185 194 Data Out DSP56364 Technical Data, Rev. 4.1 162 174 195 AA0477 Freescale Semiconductor ...

Page 53

... Serial Host Interface SPI Protocol Timing Table 3-17 Serial Host Interface SPI Protocol Timing No. Characteristics 140 Tolerable spike width on clock or data in 141 Minimum serial clock cycle = t 142 Serial clock high period Freescale Semiconductor 157 163 162 165 189 Figure 3-17 DRAM Refresh Access Filter Mode Mode — ...

Page 54

... — — — — — — 102 102 — 189 189 — — MAX{(20 — C MAX{(40 — C 2.5×T +10 35 — C 2.5×T +30 55 — C 2.5×T +50 75 — — 9 — 9 Freescale Semiconductor Unit ...

Page 55

... HREQ in assertion to first SCK edge 162 HREQ in deassertion to last SCK sampling edge (HREQ in set-up time) (CPHA = 1) 163 First SCK edge to HREQ in not asserted (HREQ in hold time) Note: Periodically sampled, not 100% tested Freescale Semiconductor Filter Mode Mode Master/ Bypassed Slave Narrow ...

Page 56

... HREQ (Input) 3-40 143 142 144 142 144 143 148 149 MSB Valid 152 MSB 163 Figure 3-18 SPI Master Timing (CPHA = 0) DSP56364 Technical Data, Rev. 4.1 141 144 141 144 149 LSB Valid 153 LSB AA0271 Freescale Semiconductor ...

Page 57

... SS (Input) SCK (CPOL = 0) (Output) SCK (CPOL = 1) (Output) MISO (Input) MOSI (Output) 161 HREQ (Input) Freescale Semiconductor 143 142 144 142 144 143 148 149 MSB Valid 152 MSB 162 163 Figure 3-19 SPI Master Timing (CPHA = 1) DSP56364 Technical Data, Rev. 4.1 ...

Page 58

... MSB 148 149 MSB Valid 157 Figure 3-20 SPI Slave Timing (CPHA = 0) DSP56364 Technical Data, Rev. 4.1 141 147 144 160 141 144 151 LSB 149 LSB Valid 159 AA0273 Freescale Semiconductor ...

Page 59

... SS (Input) SCK (CPOL = 0) (Input) 146 SCK (CPOL = 1) (Input) 150 MISO (Output) MOSI (Input) HREQ (Output) Freescale Semiconductor 143 142 144 142 144 143 152 152 MSB 148 149 MSB Valid 157 Figure 3-21 SPI Slave Timing (CPHA = 1) DSP56364 Technical Data, Rev. 4.1 ...

Page 60

... C 300 b — 100 — — 0.0 0.9 — 0.6 — 400 — 400 — 28.5 — — 39.7 — — 61.0 — — 0.0 — Freescale Semiconductor Unit kHz μs μs μs μs μ μs μs pF MHz MHz MHz ns ...

Page 61

... HRS is the prescaler rate select bit. When HRS is cleared, the fixed divide-by-eight prescaler is operational. When HRS is set, the prescaler is bypassed. HDM[7:0] are the divider modulus select bits. A divide ratio from (HDM[5: $3F) may be selected. Freescale Semiconductor 2 C Protocol Timing (continued Standard I ...

Page 62

... MSB LSB 186 182 189 184 2 Figure 3- Timing DSP56364 Technical Data, Rev. 4.1 ) and HRS = and HRS = 0 ), and the filters selected should be chosen 3-19 45ns + 135ns + 223ns + environment – 1000ns = 893ns × – = 55.8 ACK Stop 183 187 AA0275 Freescale Semiconductor ...

Page 63

... Data in hold time after RXC falling edge 441 FSR input (bl, wr) high before RXC falling 6 edge 442 FSR input (wl) high before RXC falling edge Freescale Semiconductor Symbol Expression 4 × SSICC 3 × TXC:max[3*tc; t454] 2 × − 10.0 — ...

Page 64

... Freescale Semiconductor ...

Page 65

... Periodically sampled and not 100% tested Freescale Semiconductor Symbol Expression — — ...

Page 66

... In normal mode, the output flag state is asserted for the entire frame period. 3-50 430 432 446 447 450 454 454 452 First Bit 459 453 461 458 461 460 462 Figure 3-23 ESAI Transmitter Timing DSP56364 Technical Data, Rev. 4.1 451 455 Last Bit 456 See Note AA0490 Freescale Semiconductor ...

Page 67

... RXC (Input/Output) FSR (Bit) Out FSR (Word) Out Data In 441 FSR (Bit) In FSR (Word) In Flags In HCKT SCKT (output) Freescale Semiconductor 430 431 432 433 434 437 439 First Bit 443 442 444 Figure 3-24 ESAI Receiver Timing 463 464 Figure 3-25 ESAI HCKT Timing DSP56364 Technical Data, Rev ...

Page 68

... Valid only when PLL enabled with multiplication factor equal to one. 3-52 463 465 Figure 3-26 ESAI HCKR Timing Table 3-21 GPIO Timing 1 Expression 6.75 × DSP56364 Technical Data, Rev. 4.1 Min Max Unit — 32.8 ns 4.8 — ns 10.2 — ns 1.8 — ns -1.8 65.7 — — — — — Freescale Semiconductor ...

Page 69

... Boundary scan input data setup time 505 Boundary scan input data hold time 506 TCK low to output data valid 507 TCK low to output high impedance 508 TMS, TDI data setup time Freescale Semiconductor 492 493 Valid 494 495 496 Figure 3-27 GPIO Timing 1. 2 ...

Page 70

... Characteristics = 501 502 VM VIL 503 504 Input Data Valid 506 Output Data Valid 507 506 Output Data Valid DSP56364 Technical Data, Rev. 4.1 All Frequencies Unit Min Max 25.0 — ns 0.0 44.0 ns 0.0 44.0 ns 502 VM AA0496 VIH 505 AA0497 Freescale Semiconductor ...

Page 71

... TDI TMS (Input) TDO (Output) TDO (Output) TDO (Output) Figure 3-30 Test Access Port Timing Diagram Freescale Semiconductor 508 Input Data Valid 510 Output Data Valid 511 510 Output Data Valid DSP56364 Technical Data, Rev. 4.1 JTAG Timing VIH 509 ...

Page 72

... JTAG Timing 3-56 NOTES DSP56364 Technical Data, Rev. 4.1 Freescale Semiconductor ...

Page 73

... Table 4-2show the pin/name assignments for the packages. 4.1.1 TQFP Package Description Top view of the 100-pin TQFP package is shown in package mechanical drawing is shown in Freescale Semiconductor Section 2, "Signal/Connection Figure 4-1 with its pin-outs. The 100-pin TQFP Figure 4-2. DSP56364 Technical Data, Rev. 4.1 ...

Page 74

... SS/HA2 23 MOSI/HA0 24 MISO/SDA 25 Figure 4-1 DSP56364 100-Pin Thin Quad Flat Pack (TQFP), Top View 4-2 DSP56364 100-Pin TQPF DSP56364 Technical Data, Rev. 4 A17 73 A16 72 GNDA 71 VCCA 70 A15 69 A14 68 A13 67 A12 66 VCCLQ 65 GNDQ 64 GNDA 63 VCCA 62 A11 61 VCCHQ 60 A10 GNDA 55 VCCA Freescale Semiconductor ...

Page 75

... Note: Signal names are based on configured functionality. Most pins supply a single signal. Some pins provide a signal with dual functionality, such as the MODx/IRQx pins that select an operating mode after RESET is deasserted, but act as interrupt lines during operation. Freescale Semiconductor Pin Signal Name Signal Name No ...

Page 76

... TD0 97 2 TMS 100 1 VCCA 48 24 VCCA 55 30 VCCA 63 85 VCCA 71 86 VCCC 42 90 VCCD 79 32 VCCHQ 15 28 VCCHQ 35 41 VCCHQ 61 29 VCCHQ 89 26 VCCLQ 11 7 VCCLQ 37 6 VCCLQ 66 14 VCCLQ 87 16 VCCP 31 20 VCCS 8 23 VCCS 21 17 VCCS Freescale Semiconductor ...

Page 77

... TQFP Package Mechanical Drawing Figure 4-2 DSP56364 100-pin TQFP Package Freescale Semiconductor DSP56364 Technical Data, Rev. 4.1 Pin-Out and Package Information 4-5 ...

Page 78

... Pin-Out and Package Information 4-6 DSP56364 Technical Data, Rev. 4.1 Freescale Semiconductor ...

Page 79

... To minimize temperature variation across the surface, the thermal resistance is measured from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. Freescale Semiconductor , in °C can be obtained from the following equation × ...

Page 80

... ⁄ T – CAUTION ). The suggested value for a pull-up or pull-down resistor CC power source to GND. CC and GND circuits. CC DSP56364 Technical Data, Rev. 4.1 , has been defined JT pin on the DSP and from CC and GND. CC Freescale Semiconductor and CC ...

Page 81

... Connect the unused inputs to pull-up or pull-down resistors. • Disable unused peripherals. One way to evaluate power consumption is to use a current per MIPS measurement methodology to minimize specific board effects (i.e., to compensate for measured board current not caused by the DSP). Freescale Semiconductor CCP × × I ...

Page 82

... The phase and frequency jitter performance results are only valid if the input jitter is less than the prescribed values. 5-4 Appendix A, "IBIS ⁄ ⁄ MHz = I typF2 NOTE DSP56364 Technical Data, Rev. 4.1 Model". Use the test ) ⁄ – – typF1 Freescale Semiconductor ...

Page 83

... Ordering Information Consult a Freescale Semiconductor sales office or authorized distributor to determine product availability and to place an order. Supply Part Voltage DSP56364 3.3 V Thin quad flat pack (TQFP) 1 The DSP56364 can include factory-programmed ROM. The listed ‘B’ ROM code is a generic unused ROM available to any customer ...

Page 84

... NOTES DSP56364 Technical Data, Rev. 4.1 Freescale Semiconductor ...

Page 85

... Freescale Semiconductor 3.2 56364_e.ibs e Feb 13, 2002 56364 Freescale SEMI CONDUCTOR Ltd. typ min max 45.0m 22.0m 75.0m 2.5nH 1.1nH 4.3nH 1.3pF 1.2pF 1.4pF model_name irqd_ ipad5v_io irqb_ ipad5v_io irqa_ ipad5v_io fst ipad5v_io fsr ipad5v_io sckt ipad5v_io sckr ipad5v_io vccs power ...

Page 86

... DSP56364 Technical Data, Rev. 4.1 Freescale Semiconductor ...

Page 87

... Freescale Semiconductor gpio1 ipad5v_io gpio2 ipad5v_io gpio3 ipad5v_io tdo ipad5f_io tdi ipad5f_io tck ipad5f_io tms ipad5f_io ipad5f_io I/O typ min max 1 ...

Page 88

... DSP56364 Technical Data, Rev. 4.1 Freescale Semiconductor ...

Page 89

... Freescale Semiconductor 39.460m 115.267m 39.508m 115.917m 39.552m 116.139m 39.595m 114.582m 39.634m 111.344m 39.672m 110.612m 39.708m 110.449m 39.743m 110.455m 39.777m 110.515m 39 ...

Page 90

... DSP56364 Technical Data, Rev. 4.1 Freescale Semiconductor ...

Page 91

... Freescale Semiconductor -25.585m -67.815m -25.983m -68.711m -26.415m -69.678m -26.884m -70.721m -27.390m -71.848m -27.929m -73.065m -28.487m -74.374m -29.080m -75.748m I(min) I(max) -1.875 -1 ...

Page 92

... DSP56364 Technical Data, Rev. 4.1 Freescale Semiconductor ...

Page 93

... Freescale Semiconductor I(min) I(max) ipad5i_io I/O typ min max 4.44p 3.89p 4.56p typ min max 0.0 120.0 typ min max 3 ...

Page 94

... DSP56364 Technical Data, Rev. 4.1 Freescale Semiconductor ...

Page 95

... Freescale Semiconductor 39.379m 112.374m 39.432m 113.492m 39.492m 114.510m 39.551m 115.392m 39.608m 116.061m 39.661m 116.301m 39.713m 114.763m 39.762m 111.545m 39.809m 110.833m 39.855m 110 ...

Page 96

... DSP56364 Technical Data, Rev. 4.1 Freescale Semiconductor ...

Page 97

... Freescale Semiconductor -24.570m -65.505m -24.880m -66.214m -25.217m -66.983m -25.585m -67.815m -25.983m -68.711m -26.415m -69.678m -26.884m -70.721m -27.390m -71.848m -27.929m -73.065m -28.487m -74 ...

Page 98

... DSP56364 Technical Data, Rev. 4.1 Freescale Semiconductor ...

Page 99

... Freescale Semiconductor -1.711 -1.119 -1.675 -1.793 -1.164 -1.771 -1.875 -1.209 -1.867 I(min) I(max) ipad5v_io I/O typ min max 1.96p 1 ...

Page 100

... DSP56364 Technical Data, Rev. 4.1 Freescale Semiconductor ...

Page 101

... Freescale Semiconductor 40.952m 108.448m 40.067m 109.826m 39.395m 111.106m 39.313m 112.297m 39.358m 113.400m 39.410m 114.401m 39.460m 115.267m 39.508m 115.917m 39.552m 116.139m 39.595m 114 ...

Page 102

... DSP56364 Technical Data, Rev. 4.1 Freescale Semiconductor ...

Page 103

... Freescale Semiconductor -23.411m -63.098m -23.595m -63.453m -23.801m -63.860m -24.032m -64.330m -24.288m -64.874m -24.570m -65.505m -24.880m -66.214m -25.217m -66.983m -25.585m -67.815m -25 ...

Page 104

... I(min) I(max) -20.906p -3.576u -25.110p -33.637u -29.748p -34.610p -2.883m -43.910p -14.319m -258.649p -37.029m -8.593n -9.999u -2.370m -6.612m -33.199m -95.231m -1.059 -759.489m -912.174m -1.140 -804.256m -1.007 DSP56364 Technical Data, Rev. 4.1 Freescale Semiconductor ...

Page 105

... Freescale Semiconductor -1.221 -849.071m -1.102 -1.303 -893.931m -1.197 -1.466 -983.765m -1.388 -1.548 -1.029 -1.483 -1.630 -1.074 -1.579 -1.711 -1.119 -1 ...

Page 106

... DSP56364 Technical Data, Rev. 4.1 Freescale Semiconductor ...

Page 107

... Freescale Semiconductor 73.906m 205.033m 74.304m 206.045m 74.787m 207.276m 75.368m 208.763m 76.060m 210.544m 76.878m 212.659m 77.836m 215.149m 78.948m 218.056m 80.230m 221.419m 81.694m 225 ...

Page 108

... DSP56364 Technical Data, Rev. 4.1 Freescale Semiconductor ...

Page 109

... Freescale Semiconductor -85.200m -230.481m -85.575m -231.368m -85.993m -232.336m -86.464m -233.404m -86.995m -234.592m -87.597m -235.924m -88.280m -237.426m -89.054m -239.124m -89.930m -241.046m -90.921m -243.223m -92.038m -245.685m -93.294m -248.465m -94 ...

Page 110

... I(min) I(max) -10.874p -6.086u -13.516p -53.601u -16.163p -18.939p -3.288m -29.683p -16.226m -411.332p -45.305m -15.437n -18.044u -1.613m -4.650m -11.215m -43.562m -1.026 -814.544m -753.859m -1.140 -877.750m -886.904m -1.254 -941.073m -1.021 -1.368 -1.004 -1.155 -1.483 -1.068 -1.290 DSP56364 Technical Data, Rev. 4.1 Freescale Semiconductor ...

Page 111

... Freescale Semiconductor -1.598 -1.132 -1.425 -1.713 -1.195 -1.561 -1.828 -1.259 -1.697 -2.059 -1.387 -1.969 -2.174 -1.451 -2 ...

Page 112

... DSP56364 Technical Data, Rev. 4.1 Freescale Semiconductor ...

Page 113

... Freescale Semiconductor 73.093m 202.966m 73.311m 203.524m 73.579m 204.203m 73.906m 205.033m 74.304m 206.045m 74.787m 207.276m 75.368m 208.763m 76.060m 210.544m 76.878m 212.659m 77.836m 215 ...

Page 114

... DSP56364 Technical Data, Rev. 4.1 Freescale Semiconductor ...

Page 115

... Freescale Semiconductor -84.265m -228.137m -84.551m -228.879m -84.861m -229.656m -85.200m -230.481m -85.575m -231.368m -85.993m -232.336m -86.464m -233.404m -86.995m -234.592m -87.597m -235.924m -88.280m -237.426m -89.054m -239.124m -89.930m -241.046m -90 ...

Page 116

... I(min) I(max) -10.874p -6.086u -13.516p -53.601u -16.163p -18.939p -3.288m -29.683p -16.226m -411.332p -45.305m -15.437n -18.044u -1.613m -4.650m -11.215m -43.562m -1.026 -814.544m -753.859m -1.140 -877.750m -886.904m DSP56364 Technical Data, Rev. 4.1 Freescale Semiconductor ...

Page 117

... Freescale Semiconductor -1.254 -941.073m -1.021 -1.368 -1.004 -1.155 -1.483 -1.068 -1.290 -1.598 -1.132 -1.425 -1.713 -1 ...

Page 118

... I(min) I(max) -38.990n -8.258p -9.171p -13.934u -10.084p -10.996p -3.159m -11.909p -13.160m -12.822p DSP56364 Technical Data, Rev. 4.1 Freescale Semiconductor ...

Page 119

... Freescale Semiconductor -27.650m -13.767p -61.160m -172.415p -78.852m -10.997n -96.861m -768.589n -53.501u -2.799m -22.990m -54.834m -90.181m ipadm_3st ...

Page 120

... DSP56364 Technical Data, Rev. 4.1 Freescale Semiconductor ...

Page 121

... Freescale Semiconductor 53.543m 148.757m 53.617m 148.963m 53.699m 149.186m 53.792m 149.436m 53.902m 149.725m 54.035m 150.067m 54.196m 150.479m 54.394m 150.981m 54.635m 151.594m 54.930m 152 ...

Page 122

... DSP56364 Technical Data, Rev. 4.1 Freescale Semiconductor ...

Page 123

... Freescale Semiconductor -60.117m -162.715m -60.291m -163.234m -60.467m -163.747m -60.647m -164.257m -60.832m -164.770m -61.027m -165.293m -61.234m -165.831m -61.459m -166.394m -61.704m -166.991m -61.975m -167.634m -62.278m -168.334m -62 ...

Page 124

... I(min) I(max) -11.632p -4.632u -13.966p -41.964u -16.303p -18.737p -3.014m -27.092p -14.886m -311.158p -40.029m -11.484n -13.420u -1.195m -3.451m -8.803m -37.420m DSP56364 Technical Data, Rev. 4.1 Freescale Semiconductor ...

Page 125

... Freescale Semiconductor -1.032 -773.514m -836.403m -1.126 -825.330m -945.908m -1.220 -877.220m -1.056 -1.314 -929.174m -1.166 -1.408 -981.185m -1.276 -1.503 -1.033 -1 ...

Page 126

... DSP56364 Technical Data, Rev. 4.1 Freescale Semiconductor ...

Page 127

... Freescale Semiconductor 53.343m 148.174m 53.408m 148.367m 53.475m 148.560m 53.543m 148.757m 53.617m 148.963m 53.699m 149.186m 53.792m 149.436m 53.902m 149.725m 54.035m 150.067m 54.196m 150 ...

Page 128

... DSP56364 Technical Data, Rev. 4.1 Freescale Semiconductor ...

Page 129

... Freescale Semiconductor -59.585m -161.086m -59.766m -161.644m -59.942m -162.186m -60.117m -162.715m -60.291m -163.234m -60.467m -163.747m -60.647m -164.257m -60.832m -164.770m -61.027m -165.293m -61.234m -165.831m -61 ...

Page 130

... I(min) I(max) -11.632p -4.632u -13.966p -41.964u -16.303p -18.737p -3.014m -27.092p -14.886m -311.158p -40.029m -11.484n -13.420u -1.195m -3.451m DSP56364 Technical Data, Rev. 4.1 Freescale Semiconductor ...

Page 131

... Freescale Semiconductor -8.803m -37.420m -1.032 -773.514m -836.403m -1.126 -825.330m -945.908m -1.220 -877.220m -1.056 -1.314 -929.174m -1.166 -1.408 -981.185m -1.276 -1 ...

Page 132

... DSP56364 Technical Data, Rev. 4.1 Freescale Semiconductor ...

Page 133

... Freescale Semiconductor 53.135m 147.560m 53.207m 147.772m 53.276m 147.976m 53.343m 148.174m 53.408m 148.367m 53.475m 148.560m 53.543m 148.757m 53.617m 148.963m 53.699m 149.186m 53.792m 149 ...

Page 134

... DSP56364 Technical Data, Rev. 4.1 Freescale Semiconductor ...

Page 135

... Freescale Semiconductor -59.015m -159.295m -59.211m -159.914m -59.401m -160.510m -59.585m -161.086m -59.766m -161.644m -59.942m -162.186m -60.117m -162.715m -60.291m -163.234m -60.467m -163.747m -60.647m -164.257m -60 ...

Page 136

... I(min) I(max) -11.632p -4.632u -13.966p -41.964u -16.303p -18.737p -3.014m -27.092p -14.886m -311.158p -40.029m -11.484n -13.420u DSP56364 Technical Data, Rev. 4.1 Freescale Semiconductor ...

Page 137

... Freescale Semiconductor -1.195m -3.451m -8.803m -37.420m -1.032 -773.514m -836.403m -1.126 -825.330m -945.908m -1.220 -877.220m -1.056 -1.314 -929.174m -1.166 -1 ...

Page 138

... DSP56364 Technical Data, Rev. 4.1 Freescale Semiconductor ...

Page 139

... Freescale Semiconductor 53.060m 147.338m 53.135m 147.560m 53.207m 147.772m 53.276m 147.976m 53.343m 148.174m 53.408m 148.367m 53.475m 148.560m 53.543m 148.757m 53.617m 148.963m 53.699m 149 ...

Page 140

... DSP56364 Technical Data, Rev. 4.1 Freescale Semiconductor ...

Page 141

... Freescale Semiconductor -58.812m -158.650m -59.015m -159.295m -59.211m -159.914m -59.401m -160.510m -59.585m -161.086m -59.766m -161.644m -59.942m -162.186m -60.117m -162.715m -60.291m -163.234m -60.467m -163.747m -60 ...

Page 142

... I(min) I(max) -11.632p -4.632u -13.966p -41.964u -16.303p -18.737p -3.014m -27.092p -14.886m -311.158p -40.029m -11.484n DSP56364 Technical Data, Rev. 4.1 Freescale Semiconductor ...

Page 143

... R_load=10000ohms | R_load was connected to ground for Ramp_up test and power for Ramp_dn test | |End model [End] Freescale Semiconductor -13.420u -1.195m -3.451m -8.803m -37.420m -1.032 -773.514m -836.403m -1.126 -825.330m -945.908m -1.220 -877.220m -1.056 -1.314 -929.174m -1 ...

Page 144

... A-60 NOTES DSP56364 Technical Data, Rev. 4.1 Freescale Semiconductor ...

Page 145

... PLL 4 power consumption 3 thermal 1 DRAM out of page wait states selection guide 27 Freescale Semiconductor out of page and refresh timings 11 wait states 31 15 wait states 33 4 wait states 27 8 wait states 29 Page mode read accesses 26 wait states selection guide 17 ...

Page 146

... Port C 9 Power 2 power consumption design considerations 3 R recovery from Stop state using IRQA 11, 12 RESET 6 Reset timing Serial Audio Interface (ESAI) 3 Serial Host Interface 7 Serial Host Interface (SHI) 3 SHI 7 signal groupings 1 signals 1 SRAM DSP56364 Technical Data, Rev. 4.1 Freescale Semiconductor ...

Page 147

... General Purpose I/O (GPIO) Timing 47 OnCE™ (On Chip Emulator) Timing 47 Serial Host Interface (SHI) SPI Protocol Tim- ing 37 Serial Host Interface (SHI) Timing 37 timing interrupt 7 mode select 7 Reset 7 Stop 7 TQFP pin list by number 3 pin-out drawing (top) 1 Freescale Semiconductor DSP56364 Technical Data, Rev. 4.1 Index-3 ...

Page 148

... Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use ...