DSPA56371AF150B Freescale Semiconductor, DSPA56371AF150B Datasheet - Page 4

• Manufacturer Part Number: DSPA56371AF150B
• Manufacturer: Freescale Semiconductor

Specifications of DSPA56371AF150B

• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 150MHz
• Mips: 150
• Device Input Clock Speed: 150MHz
• Program Memory Size: 192KB
• Operating Supply Voltage (typ): 1.25/3.3V
• Operating Supply Voltage (min): 1.2/3.14V
• Operating Temp Range: -40C to 115C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: LQFP
• Lead Free Status / Rohs Status: Compliant

DSP56371 Overview
2.3
This section defines the DSP56371 audio processor architecture. The audio processor is composed of the
following units:
Memory sizes in the block diagram are defaults. Memory may be differently partitioned, according to the
memory mode of the chip. See
2.4
The DSP56300 core provides the following functional blocks:
4
•
•
•
•
•
•
•
•
•
•
•
•
— Enhanced Serial Audio Interface I (ESAI_1): up to 4 receivers and up to 6 transmitters, master
— Serial Host Interface (SHI): SPI and I
— Triple Timer module (TEC).
— 11 dedicated GPIO pins
— Digital Audio Transmitter (DAX): 1 serial transmitter capable of supporting the SPDIF,
— Pins of unused peripherals (except SHI) may be programmed as GPIO lines
The DSP56300 core is composed of the Data ALU, Address Generation Unit, Program Controller,
DMA Controller, Memory Module Interface, Peripheral Module Interface and the On-Chip
Emulator (OnCE). The DSP56300 core is described in the document <st-blue>DSP56300 24-Bit
Digital Signal Processor Family Manual, Motorola publication DSP56300FM/AD.
Phased Lock Loop and Clock Generator
Memory modules
Peripheral modules. The peripheral modules are defined in the following sections.
Data arithmetic logic unit (Data ALU)
Address generation unit (AGU)
Program control unit (PCU)
DMA controller (with six channels)
Instruction patch controller
PLL-based clock oscillator
OnCE module
Memory
DSP56371 Audio Processor Architecture
DSP56300 Core Functional Blocks
slave. I
protocols
or slave. I
protocols
10-word receive FIFO, support for 8, 16 and 24-bit words
IEC958, CP-340 and AES/EBU digital audio formats
2
S, left justified, right justified, Sony, AC97, network and other programmable
2
S, left justified, right justified, Sony, AC97, network and other programmable
Section 2.4.7 On-Chip Memory
DSP56371 Data Sheet, Rev. 4.1
2
C protocols, multi master capability in I
for more details about memory size.
Freescale Semiconductor
2
C mode,