21554AA Intel, 21554AA Datasheet
21554AA
Specifications of 21554AA
21554AA Summary of contents
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PCI-to-PCI Non-Transparent Bridge Evaluation Board User’s Guide January 2001 Order Number: 273475-001 ...
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... PCI-to-PCI Non-Transparent Bridge Evaluation Board Information in this document is provided in connection with Intel rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel merchantability, or infringement of any patent, copyright or other intellectual property right ...
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Contents 1 Introduction ............................................................................................................................. 1-5 1.1 Overview ......................................................................................................................... 1-5 1.2 Features............................................................................................................................ 1-5 1.3 Major Components .......................................................................................................... 1-6 1.3.1 Local or Secondary Bus Connectors................................................................. 1-6 1.3.2 Test Point Pods.................................................................................................. 1-7 1.3.3 Jumpers ............................................................................................................. 1-7 1.3.4 Switch Packs ..................................................................................................... 1-7 1.3.5 Devices.............................................................................................................. ...
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PCI-to-PCI Non-Transparent Bridge Evaluation Board Figures 1-1 Major Components .......................................................................................................... 1-6 1-2 Switches........................................................................................................................... 1-8 1-3 Zero-Ohm Resistor Jumpers .......................................................................................... 1-10 1-4 Local PCI Slot Numbering ............................................................................................ 1-12 1-5 One Local Bus Option Card .......................................................................................... 1-14 1-6 Two Local Bus ...
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... Overview The DE1B55401 is a PCI expansion board that is used to evaluate the operation of the 21554 when used as a gateway to an intelligent subsystem. The subsystem can use a variety of PCI devices and local processors. The DE1B55401 can be used to perform the following functions: • ...
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Introduction 1.3 Major Components Figure 1-1 shows the major components on the DE1B55401. Figure 1-1. Major Components E7, E8 Parallel ROM Address Latches E5 - Parallel ROM J24 - J25 Jumpers E7, E8 Initialization Switches 1.3.1 ...
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Test Point Pods The DE1B55401’s 64 test points are presented in 16-pin pods, which are header type connectors. Each pod contains eight (8) individual test point pairs. There are 15 pods on the board. The pods are arranged on ...
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Introduction 1.4 Switch Settings There are three 5-switch switch packs on the DE1B55401. Each switch is single-pole, double throw. The switche packs are in dual-in-line (DIP) packages designated J19, J20, and J21. The switches are identified as SW1 through SW5. ...
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Table 1-1 describes operation of the switches. The switches should be set before powering up the system. • The up position means switch points toward the local sockets. • Down means the switch points toward the card edge. Table 1-1. ...
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Introduction 1.6 Clock Configuration Figure 1-3 shows the location of the zero-ohm jumper resistors that control the clock and clamping voltages. Note: The signals p_clk and s_clk_o are not wired to scope pod positions for improved signal integrity. Table 1-3 ...
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Table 1-3 shows the connections required to allow observation of these signals at scope pod connector pins and shows the resistors and jumpers needed to configure the clocks. Table 1-3. Clock Configuration Jumpers Connects p_clk to test pod J18 pin ...
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Introduction 1.8 Local Bus Slot Numbering and IDSEL Mapping Figure 1-4 shows that the PCI local bus option card slots are mapped to PCI device numbers 4,5,6 and 7. The local bus lines s_ad<24> and s_ad<31:28> are used as local ...
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Interrupt Routing 1.9 Table 1-5 shows the ORing of interrupts. 12 interrupts are connected to the secondary bus PCI slots but four (4) are driven to the card edge. The 12 incoming interrupts must be combined in accordance with the ...
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Introduction 1.10 Typical Configurations Figure 1-5 shows the DE1B55401 with one local bus option card. Figure 1-5. One Local Bus Option Card (J101) (J102) 1-14 ADD-IN CARD E9 C82 C74 E8 E7 C75 C84 C55 E5 J18 J14 J12 C89 ...
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Figure 1-6 shows the DE1B55401 with two local bus option cards. Note: The option card can be either 32-bit or 64-bit. Figure 1-6. Two Local Bus Option Cards (J101) 21554 PCI-to-PCI Non-Transparent Bridge Evaluation Board User’s Guide ADD-IN CARD J101 ...
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Operation and Installation This chapter provides information about the DE1B55401 specifications, hardware, and software requirements. It also describes how to install the DE1B55401. 2.1 Specifications The physical and power specifications for the DE1B55401 are: Dimensions: • Height: 20.2 cm (8.0 ...
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Operation and Installation 2.3 Software Requirements The DE1B55401 is shipped with the SROM and parallel ROM programmed during module test. One version of test pattern in the parallel ROM will print the 21554 banner to the screen during system boot. ...
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Flash ROM Programming Dbflash.exe is an MSDOS based program that allows the flash ROM attached to the 21554 to be erased and updated with new images. When dbflash.exe is run on a system that has a 21554 installed on ...
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Operation and Installation 2.4 DE1B55401 Installation Procedure Figure 1-1 Illustrates the DE1B55401 and shows the location of components referred to in this section. Install the DE1B55401 as follows: 1. Power down the host system that will contain the DE1B55401. 2. ...
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... PCI interface as defined be the PICMG PCI-ISA interface specification. The DE1B55401can support an intelligent subsystem on the local bus. The intelligent subsystem is architecture independent. The 21554 can interface to the PCI interface of any intelligent subsystem. The J101 connector has the capability of accepting an intelligent controller. Table 3-1 details the jumper options necessary for this mode of operation ...
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... Central Function and Arbiter Control Table 3-3 specifies how to configure the DE1B55401 as an external or central arbitrator. When an intelligent subsystem is on the local bus, the DE1B55401 can operate using an external arbiter agent or the 21554 Central Function mode internal arbitration logic. Table 3-3. ...
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Signal and Default Information A.1 Test Pod Pin Outs Test points are accessible through board mounted Header type connectors, which are referred to as pods. The following tables give the schematic name of the signal that can be found at ...
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Signal and Default Information Table A-2 associates the pod pin numbers to the extended secondary bus address and data lines. See Figure 1-1 on page 1-6 Table A-2. Extended Secondary Address and Data Pods Pod Pin Number a. Table A-3 ...
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A.2 Factory Default Switch and Jumper Configuration The DEB55401 is configured at the factory for normal or typical operation. • Table A-4 gives the factory configuration for the stake-pin jumpers. Table A-4. Stake-Pin Jumpers • Table A-5 gives the factory ...
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