DS90C3202VS National Semiconductor, DS90C3202VS Datasheet - Page 5

• Manufacturer Part Number: DS90C3202VS
• Manufacturer: National Semiconductor

Specifications of DS90C3202VS

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / Rohs Status: Not Compliant

Symbol
CLHT
CHLT
CLHT
Programmable
adjustment
CHLT
Programmable
adjustment
RCOP
RCOH
RCOL
RSRC
RHRC
RSRC/RHRC
Programmable
Adjustment
RPLLS
RPDD
RPDL
RITOL
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Note 8: Specification is guaranteed by characterization.
Note 9: A Clock Unit Symbol (T) is defined as 1/ (Line rate of RCLK). E.g. For Line rate of RCLK at 85MHz, 1 T = 11.76ns
Note 10: A Unit Interval (UI) is defined as 1/7th of an ideal clock period (RCLK/7). E.g. For an 11.76ns clock period (85MHz), 1 UI = 1.68ns
LVCMOS/LVTTL Low-to-High Transition
Time, C
Register addr 28d/1ch,
bit [2] (RCLK)=0b (Default),
bit [1] (RXE) =0b (Default),
bit [0] (RXO) =0b (Default)
LVCMOS/LVTTL High-to-Low Transition
Time, C
Register addr 28d/1ch,
bit [2] (RCLK)=0b (Default),
bit [1] (RXE) =0b (Default),
bit [0] (RXO) =0b (Default)
LVCMOS/LVTTL Low-to-High Transition
Time, C
Register addr 28d/1ch,
bit [2] (RCLK)=1b (Default),
bit [1] (RXE) =1b (Default),
bit [0] (RXO) =1b (Default)
LVCMOS/LVTTL High-to-Low Transition
Time, C
Register addr 28d/1ch,
bit [2] (RCLK)=0b (Default),
bit [1] (RXE) =0b (Default),
bit [0] (RXO) =0b (Default)
RCLK OUT Period (Figures 11, 12) (Note 8)
RCLK OUT High Time (Figures 11, 12)
RCLK OUT Low Time (Figures 11, 12)
RxOUT Setup to RCLK OUT (Figures 11, 12) (Notes 8, 9)
Register addr 29d/1dh [2:1]= 00b (Default)
RxOUT Hold to RCLK OUT (Figures 11, 12) (Notes 8, 9)
Register addr 29d/1dh [2:1]= 00b (Default)
Register addr 29d/1dh [2:1] = 01b, (Figures 13, 14)
(Notes 2, 10)
RSRC increased from default by 1UI
RHRC decreased from default by 1UI
Register addr 29d/1dh [2:1] = 10b, (Figures 13, 14)
(Notes 2, 10)
RSRC decreased from default by 1UI
RHRC increased from default by 1UI
Register addr 29d/1dh [2:1] = 11b, (Figures 13, 14)
(Notes 2, 10)
RSRC increased from default by 2UI
RHRC decreased from default by 2UI
Receiver Phase Lock Loop Set (Figure 6)
Receiver Powerdown Delay (Figure 7)
Receiver Propagation Delay — Latency (Figure 8)
Receiver Input Tolerance
(Figures 10, 16) (Notes 8, 10)
L
L
L
L
= 8pF, (Figure 5) (Note 8)
= 8pF, (Figure 5) (Note 8)
= 8pF, (Figure 5) (Note 8)
= 8pF, (Figure 5) (Note 8)
Parameter
5
Rx clock out
Rx data out
Rx clock out
Rx data out
Rx clock out
Rx data out
Rx clock out
Rx data out
8–135 MHz
Rx clock out
Rx clock out
V
V
CM
ID
Condition/
Reference
= 350mV
= 1.25V,
0.4T
0.4T
2.60
3.60
Min
7.4
+1UI /
+2UI /
-1UI /
+1UI
0.5T
0.5T
0.5T
0.5T
1.45
2.40
1.35
2.40
2.45
3.40
2.35
3.40
-1UI
-2UI
Typ
T
4*RCLK
Max
2.10
3.50
2.20
3.60
0.6T
0.6T
0.25
125
100
10
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Units
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UI