ATA5811-PLQX Atmel, ATA5811-PLQX Datasheet - Page 52

• Manufacturer Part Number: ATA5811-PLQX
• Manufacturer: Atmel

Specifications of ATA5811-PLQX

• Operating Temperature (min): -40C
• Operating Temperature (max): 105C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 7mm
• Product Height (mm): 0.9mm
• Product Length (mm): 7mm
• Lead Free Status / Rohs Status: Compliant

Bit-check Mode
Configuration the Bit-check
Figure 42. Timing Diagram for Complete Successful Bit-check (Number of Checked Bits: 3)
52
RX_ACTIVE
ATA5811/ATA5812 [Preliminary]
Demod_Out
Bit check
Start-up mode
T
Startup_Sig_Proc
In Bit-check mode the incoming data stream is examined to distinguish between a valid
signal from a corresponding transmitter and signals due to noise. This is done by subse-
quent time frame checks where the distance between 2 signal edges are continuously
compared to a programmable time window. The maximum count of this edge to edge
test before the transceiver switches to receiving mode is also programmable.
Assuming a modulation scheme that contains 2 edges per bit, two time frame checks
are verifying one bit. This is valid for Manchester, Bi-phase and most other modulation
schemes. The maximum count of bits to be checked can be set to 0, 3, 6 or 9 bits via the
variable N
respectively. If N
receiving mode due to noise. In the presence of a valid transmitter signal, the Bit-check
takes less time if N
is not dependent on N
successful.
According to Figure 43, the time window for the Bit-check is defined by two separate
time limits. If the edge to edge time t
and the upper Bit-check limit T
limit T
switches to sleep mode.
Figure 43. Valid Time Window for Bit-check
1/2 Bit
Lim_min
Demod_Out
Bit-check
or exceeds T
1/2 Bit
Bit-check
in control register 5. This implies 0, 6, 12 and 18 edge to edge checks
Bit-check
Bit-check
is set to a higher value, the transceiver is less likely to switch to
Bit-check mode
1/2 Bit
is set to a lower value. In RX polling mode, the Bit-check time
Lim_max
T
Bit-check
. Figure 42 shows an example where 3 bits are tested
Lim_max
Bit check ok
, the Bit-check will be terminated and the transceiver
1/2 Bit
, the check will be continued. If t
ee
T
T
is in between the lower Bit-check limit T
Lim_min
Lim_max
t
ee
1/2 Bit
1/f
Sig
1/2 Bit
Receiving mode
ee
is smaller than
4689B–RKE–04/04
Lim_min