GAL26V12C-20LJ Lattice, GAL26V12C-20LJ Datasheet - Page 14

• Manufacturer Part Number: GAL26V12C-20LJ
• Description: SPLD - Simple Programmable Logic Devices HI PERF E2CMOS PLD
• Manufacturer: Lattice

Specifications of GAL26V12C-20LJ

• Logic Family: GAL
• Number Of Macrocells: 12
• Maximum Operating Frequency: 62.5 MHz
• Number Of Programmable I/os: 12
• Delay Time: 20 ns
• Operating Supply Voltage: 5 V
• Supply Current: 105 mA
• Maximum Operating Temperature: + 75 C
• Minimum Operating Temperature: 0 C
• Package / Case: PLCC-28
• Mounting Style: SMD/SMT
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Lead Free Status / Rohs Status: No

An electronic signature is provided in every GAL26V12 device.
It contains 64 bits of reprogrammable memory that can contain
user-defined data. Some uses include user ID codes, revision
numbers, or inventory control. The signature data is always
available to the user independent of the state of the security cell.
A security cell is provided in every GAL26V12 device to prevent
unauthorized copying of the array patterns. Once programmed,
this cell prevents further read access to the functional bits in the
device. This cell can only be erased by re-programming the
device, so the original configuration can never be examined once
this cell is programmed. The Electronic Signature is always avail-
able to the user, regardless of the state of this control cell.
GAL26V12 devices are designed with an on-board charge pump
to negatively bias the substrate. The negative bias minimizes the
potential for latch-up caused by negative input undershoots.
Additionally, outputs are designed with n-channel pull-ups instead
of the traditional p-channel pull-ups in order to eliminate latch-up
due to output overshoots.
GAL devices are programmed using a Lattice-approved Logic
Programmer, available from a number of manufacturers (see the
the GAL Development Tools section). Complete programming of
the device takes only a few seconds. Erasing of the device is
transparent to the user, and is done automatically as part of the
programming cycle.
SECURITY CELL
ELECTRONIC SIGNATURE
LATCH-UP PROTECTION
DEVICE PROGRAMMING
13
When testing state machine designs, all possible states and state
transitions must be verified in the design, not just those required
in the normal machine operations. This is because certain events
may occur during system operation that throw the logic into an
illegal state (power-up, line voltage glitches, brown-outs, etc.). To
test a design for proper treatment of these conditions, a way must
be provided to break the feedback paths, and force any desired
(i.e., illegal) state into the registers. Then the machine can be
sequenced and the outputs tested for correct next state condi-
tions.
The GAL26V12 device includes circuitry that allows each regis-
tered output to be synchronously set either high or low. Thus, any
present state condition can be forced for test sequencing. If
necessary, approved GAL programmers capable of executing test
vectors perform output register preload automatically.
GAL26V12 devices are designed with TTL level compatible in-
put buffers. These buffers have a characteristically high imped-
ance, and present a much lighter load to the driving logic than bi-
polar TTL devices.
OUTPUT REGISTER PRELOAD
INPUT BUFFERS
Specifications GAL26V12